Apparatus and method for protecting from illegal copy

• US 20060119378A1
• Filed: 12/01/2005
• Published: 06/08/2006
• Est. Priority Date: 12/02/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Tonami, Masahiro
• Granted Patent: US 7,262,629 B2
• Time in Patent Office: Days
• US Class Current: 326/8
• CPC Class Codes: G06F 21/14 against software analysis or reverse engineering, e.g. by obfuscation
• CPC Class Codes: H03K 17/00 Electronic switching or gating, i.e. not by contact-making and –breaking gated amplifiers H03F3/72; switching arrangements for exchange systems using static devices H04Q3/52
• CPC Class Codes: H03K 3/00 Circuits for generating electric pulses; Monostable, bistable or multistable circuits H03K4/00 takes precedence; for digital function generators in computers G06F1/02

Abstract

A copy protection circuit to prevent illegal copy of a circuit configuration data when the user circuit data is read out and transferred from a storage device to a rewritable gate array (FPGA), includes a control circuit, a data generating circuit and a data switch circuit. The control circuit controls transfer of the circuit configuration data from the storage device to the FPGA, and the data generating circuit generates pseudo circuit configuration data. The data switch circuit transfers to the FPGA, the circuit configuration data read out from the storage circuit and the pseudo circuit configuration data outputted from the data generating circuit. The data switch circuit transfers to the FPGA the circuit configuration data which is less than a data amount that the FPGA needs, and then the pseudo circuit configuration data.

Claims

1. A copy protection circuit to prevent illegal copy of a circuit configuration data when the user circuit data is read out and transferred from a storage device to a rewritable gate array (FPGA), comprising:

a control circuit configured to control transfer of said circuit configuration data from said storage device to said FPGA;

a data generating circuit configured to generate pseudo circuit configuration data; and

a data switch circuit configured to transfer to said FPGA, said circuit configuration data read out from said storage circuit and said pseudo circuit configuration data outputted from said data generating circuit,

wherein said data switch circuit transfers to said FPGA said circuit configuration data which is less than a data amount that said FPGA needs, and then said pseudo circuit configuration data.

2. The copy protection circuit according to claim 1, wherein said data generating circuit generates said pseudo circuit configuration data based on a preset data.

3. The copy protection circuit according to claim 1, wherein said data generating circuit generates said pseudo circuit configuration data based on a data that has been stored in said storage circuit.

4. The copy protection circuit according to claim 1, wherein said pseudo circuit configuration data contains at least a part of said circuit configuration data.

5. The copy protection circuit according to claim 1, wherein said storage device has stored said circuit configuration data which contains a first circuit configuration data and a second circuit configuration data,

said switch circuit transfers said first circuit configuration data read out from said storage device and then said pseudo circuit configuration data to said FPGA,

said control circuit determines whether or not transfer of said second circuit configuration data to said FPGA is permitted, based on a confirmation signal outputted from a first circuit generated based on said first circuit configuration data set in said FPGA, and

said control circuit controls said switch circuit to transfer said second circuit configuration data read out from said storage circuit and then said pseudo circuit configuration data to said FPGA, based on the determination result.

6. The copy protection circuit according to claim 5, further comprising:

a decoding circuit configured to decode said confirmation signal, said confirmation signal contains an encoded data; and

a determining circuit configured to determine validity of said first circuit configuration data based on the decoded confirmation signal,

wherein said control circuit controls said switch to transfer said second circuit configuration data to said FPGA, when the determination result indicates validity.

7. The copy protection circuit according to claim 5, wherein said circuit configuration data contains a third circuit configuration data between

said first circuit configuration data and said second circuit configuration data, and said circuit data generating circuit generates said pseudo circuit configuration data based on said third circuit configuration data.

8. A copy protection system comprising:

a gate array (FPGA) that a circuit configuration is rewritable by a user;

a storage device configured to store a plurality of circuit configuration data used to define the circuit configuration of said FPGA; and

a copy protection circuit configured to transfer said plurality of circuit configuration data to said FPGA,

wherein said copy protection circuit comprises;

a control circuit configured to control transfer of each of said plurality of circuit configuration data to said FPGA; and

a data generating circuit configured to generate a pseudo circuit configuration data, and

said copy protection circuit determines whether to permit each of said plurality of circuit configuration data to be transferred to said FPGA, reads out each of said plurality of circuit configuration data from said storage device to transfer to said FPGA when the transfer is permit, and then transfers said pseudo circuit configuration data to said FPGA.

9. The copy protection system according to claim 8, wherein a first one of said plurality of circuit configuration data has a code string, said copy protection circuit:

receives said code string from said FPGA after transferring said first circuit configuration data and said pseudo circuit configuration data to said FPGA,

determines validity of said first circuit configuration data based on the received code string, and

reads out a second one of said plurality of circuit configuration data to transfer to said FPGA, when the validity is confirmed.

10. The copy protection system according to claim 9, wherein said code string is encoded and transmitted from said FPGA.

11. The copy prevention system according to claim 8, wherein said storage device comprises a semiconductor storage device.

12. The copy protection system according to claim 8, wherein said copy protection circuit comprises a gate array programmed by a semiconductor vender.

13. A method of preventing an illegal copy of a circuit configuration data for a gate array (FPGA) that a circuit configuration is rewritable by a user, comprising:

transferring a first one of a plurality of circuit configuration data stored in a storage device to said FPGA;

generating a pseudo circuit configuration data;

transferring said pseudo circuit configuration data to said FPGA after said circuit configuration data is transferred from said storage device to said FPGA; and

determining whether to transfer a second one of said plurality of circuit configuration data to said FPGA.

14. The copy protecting method according to claim 13, wherein said first circuit configuration data contains a code string,

said determining comprises:

confirming validity of said first circuit configuration data based on said code string which is outputted from a first circuit set in said FPGA based on said first circuit configuration data; and

transferring said second circuit configuration data to said FPGA when the validity is confirmed.

15. The copy protecting method according to claim 14, wherein said code string is encoded and outputted from said first circuit.

16. The copy protecting method according to claim 13, wherein said generating comprises:

generating said pseudo circuit configuration data based on a preset data.

17. The copy protecting method according to claim 13, wherein said generating comprises:

generating said pseudo circuit configuration data containing at least a part of said plurality of circuit configuration data.