Multi-frequency clock synthesizer
First Claim
1. An apparatus comprising:
- a multi-frequency phase-locked loop (PLL) circuit including a feedback divider circuit;
a storage to store a plurality of values;
at least one input terminal coupled to select a particular one of the stored values; and
wherein the multi-frequency PLL circuit is coupled to output one of a plurality of selectable output signals having an arbitrary frequency relationship to each other, each of the selectable output signals corresponding to one of the stored values, the one of the plurality of the selectable output signals that is output by the PLL circuit corresponding to the particular one of the stored values, the particular one of the stored values being coupled to determine, at least in part, a divide ratio of the feedback divider circuit.
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Accused Products
Abstract
A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.
135 Citations
34 Claims
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1. An apparatus comprising:
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a multi-frequency phase-locked loop (PLL) circuit including a feedback divider circuit;
a storage to store a plurality of values;
at least one input terminal coupled to select a particular one of the stored values; and
wherein the multi-frequency PLL circuit is coupled to output one of a plurality of selectable output signals having an arbitrary frequency relationship to each other, each of the selectable output signals corresponding to one of the stored values, the one of the plurality of the selectable output signals that is output by the PLL circuit corresponding to the particular one of the stored values, the particular one of the stored values being coupled to determine, at least in part, a divide ratio of the feedback divider circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method comprising:
selecting a frequency of an output signal from a phase-locked loop (PLL) circuit to be one of a plurality of selectable output frequencies having an arbitrary relationship to each other, the selection being determined according to a frequency select value determined by a frequency selection mechanism that utilizes at least one input terminal of a device incorporating the PLL circuit. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. An integrated circuit comprising:
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a phase-locked loop (PLL) circuit including an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator; and
means for selecting for output from the PLL circuit an output signal having one of a plurality frequencies having an arbitrary frequency relationship to each other, according to a value of one or more input terminals of the integrated circuit. - View Dependent Claims (28)
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29. An integrated circuit comprising:
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a fractional N phase-locked loop circuit including, an input for receiving a timing reference signal;
a feedback divider circuit;
a phase detector circuit coupled to the timing signal and the feedback divider circuit;
a controllable oscillator circuit coupled to the phase detector circuit;
wherein a divide ratio of the feedback divider circuit is pin programmable. - View Dependent Claims (30)
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31. A method comprising:
selecting one of a plurality of selectable output frequencies having an arbitrary relationship to each other to be output from a phase-locked loop (PLL) circuit according to control information received over a digital communications interface. - View Dependent Claims (32, 33)
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34. A line card for use in a communications system comprising:
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an integrated circuit including, a first phase-locked loop (PLL) circuit having a feedback divider circuit;
a storage to store a plurality of values;
one or more input terminals coupled to select a particular one of the stored values;
wherein the PLL circuit is coupled to output one of a plurality of selectable output signals having an arbitrary frequency relationship to each other, each of the selectable output signals corresponding to one of the stored values, the one of the plurality of the selectable output signals that is output by the first PLL circuit corresponding to the particular one of the stored values, the particular one of the stored values being coupled to determine, at least in part, a divide ratio of the feedback divider circuit;
a voltage control input to adjust a frequency of the phase-locked loop circuit output signal and wherein the voltage control input is coupled to further control the divide ratio of the feedback divider circuit according to a voltage present on the voltage control input;
a single resonator coupled directly to the integrated circuit;
a clock scaling phase locked loop including a phase detector and loop filter coupled to an output of the first phase-locked loop and a timing reference signal and coupled to provide a voltage signal coupled to the voltage control input.
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Specification