×

Multi-frequency clock synthesizer

  • US 20060119402A1
  • Filed: 11/10/2005
  • Published: 06/08/2006
  • Est. Priority Date: 05/02/2003
  • Status: Active Grant
First Claim
Patent Images

1. An apparatus comprising:

  • a multi-frequency phase-locked loop (PLL) circuit including a feedback divider circuit;

    a storage to store a plurality of values;

    at least one input terminal coupled to select a particular one of the stored values; and

    wherein the multi-frequency PLL circuit is coupled to output one of a plurality of selectable output signals having an arbitrary frequency relationship to each other, each of the selectable output signals corresponding to one of the stored values, the one of the plurality of the selectable output signals that is output by the PLL circuit corresponding to the particular one of the stored values, the particular one of the stored values being coupled to determine, at least in part, a divide ratio of the feedback divider circuit.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×