Pulse-rejecting circuit for suppressing single-event transients
First Claim
1. A circuit for hardening against single-event transients, the circuit comprising in combination:
- a delay circuit, wherein the delay circuit receives an input signal and delays the input signal by a predetermined time delay to produce a time-delayed version of the input signal;
an inverter circuit electrically coupled to the delay circuit, wherein the inverter circuit is configured to receive the input signal and the time-delayed version of the input signal, and to propagate an output signal with a corresponding output logic level only when the input signal and the time-delayed version of the input signal have equivalent input logic levels; and
an output-holding circuit electrically coupled to the inverter circuit, wherein the output-holding circuit operates to hold the output signal at the corresponding output logic level when the input signal and the time-delayed version of the input signal have opposite input logic levels.
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Abstract
A circuit for rejecting single-event transients (SETs) from logic signals is provided. The circuit includes a delay circuit, an inverter circuit, and an output-holding circuit. The delay circuit receives an input signal and delays the input signal to produce a time-delayed version of the input signal. The input signal and the time-delayed version of the input signal are fed into the inverter circuit that propagates a corresponding output signal only when the input signal and the time-delayed version of the input signal have the same logic level. If the input signal or the time-delayed version of the input signal transitions such that both input signals presented to the inverter circuit have opposite logic levels, the output-holding circuit maintains the output signal in its previous state.
68 Citations
22 Claims
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1. A circuit for hardening against single-event transients, the circuit comprising in combination:
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a delay circuit, wherein the delay circuit receives an input signal and delays the input signal by a predetermined time delay to produce a time-delayed version of the input signal;
an inverter circuit electrically coupled to the delay circuit, wherein the inverter circuit is configured to receive the input signal and the time-delayed version of the input signal, and to propagate an output signal with a corresponding output logic level only when the input signal and the time-delayed version of the input signal have equivalent input logic levels; and
an output-holding circuit electrically coupled to the inverter circuit, wherein the output-holding circuit operates to hold the output signal at the corresponding output logic level when the input signal and the time-delayed version of the input signal have opposite input logic levels. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21)
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16. A pulse-rejecting circuit for suppressing single-event transients in logic signals, the pulse-rejecting circuit comprising:
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a delay circuit, wherein the delay circuit receives an input signal and produces a time-delayed version of the input signal, the time-delayed version being delayed in time with respect to the input signal by a predetermined time delay that is selected to be longer than a maximum duration of a transient pulse carried within the input signal;
an inverter circuit having a first input, a second input electrically coupled to the delay circuit, and an output, wherein the inverter circuit is configured to receive the input signal via the first input and the time-delayed version of the input signal via the second input, and wherein the inverter circuit operates to propagate an output signal with a corresponding output logic level onto the output only when the input signal on the first input and the time-delayed version of the input signal on the second input have equivalent input logic levels; and
an output-holding circuit electrically coupled to the output of the inverter circuit, the output-holding circuit being operative to hold the output signal at the corresponding output level when the input signal at the first input or the delayed version of the input signal at the second input experiences a pulse-induced signal transition that causes the input signal and the delayed version of the input signal to have opposite input logic levels. - View Dependent Claims (17, 18, 19, 20, 22)
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Specification