High frequency receiver preamplifier with CMOS rail-to-rail capability

• US 20060119429A1
• Filed: 12/02/2004
• Published: 06/08/2006
• Est. Priority Date: 12/02/2004
• Status: Active Grant

• Current Assignee: Karmic Design-USA, LLC
• Original Assignee: FTD Solutions Pte., Ltd.
• Inventors: Lim, Hong Sair
• Granted Patent: US 7,777,568 B2
• Time in Patent Office: Days
• US Class Current: 330/253
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/45054 the cascode stage of the cascode dif amp being a current mirror
• CPC Class Codes: H03F 2203/45496 the CSC comprising one or more extra resistors
• CPC Class Codes: H03F 2203/45641 the LC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/45219 Folded cascode stages
• CPC Class Codes: H03F 3/45224 Complementary Pl types having parallel inputs and being supplied in parallel

Abstract

A folded cascade receiver amplifier with constant gain has inputs coupled to PMOS and NMOS differential transistors pairs with scaled geometries. The transconductance of both PMOS and NMOS transistors is the same whether the common mode input voltage is low or high. In a first version the transconductance of both PMOS and NMOS differential transistor pairs is reduced when the common mode input voltage is at mid-rail. Resistive means between current sources and the sources of the PMOS and NMOS transistor pairs force the current source transistors into the triode region of operation. A second version insures a constant voltage gain through control means which maintain a constant ratio of the transconductance of the output stage transistors versus the PMOS and NMOS differential transistor pairs when active.

Claims

1. A folded cascode preamplifier, comprising:

an open-loop high frequency differential amplifier with PMOS and NMOS transistor pairs coupled to differential inputs, where first and second resistive means are coupled in series with first and second current sources and the sources of each of said PMOS and NMOS transistor pairs, respectively, to force transistors of said first and second current sources into the triode region of their operation thus reducing the tail current of both PMOS and NMOS transistor pairs when active at the same time, such that when either PMOS and NMOS transistor pair is active, the overall transconductance is the same as when both PMOS and NMOS transistor pairs are active, independent of the common mode input voltage applied to said differential inputs, where the drains of both PMOS and NMOS transistor pairs are in communication with differential summing outputs; and

an output stage coupled to said differential summing outputs to amplify the currents summed at said differential summing outputs.

2. The folded cascode preamplifier of claim 1, wherein said sources of said PMOS differential input pair in series with said first resistive means and said first current source is in communication with a positive terminal of a power supply.

3. The folded cascode preamplifier of claim 1, wherein said sources of said NMOS differential input pair in series with said second resistive means and said second current source is in communication with a negative terminal of a power supply.

4. The folded cascode preamplifier of claim 1, wherein PMOS and NMOS transistors of said PMOS and NMOS differential input pairs are scaled such that the transconductance of said PMOS and NMOS transistor is the same when active.

5. The folded cascode preamplifier of claim 1, wherein said differential summing outputs sum the currents of said PMOS and NMOS differential input pairs.

6. The folded cascode preamplifier of claim 1, wherein a low common mode input voltage activates said PMOS transistor pair.

7. The folded cascode preamplifier of claim 1, wherein a high common mode input voltage, activates said NMOS transistor pair.

8. The folded cascode preamplifier of claim 1, wherein a common mode input voltage ranging between a low and a high common mode voltage activates both said PMOS and said NMOS transistor pairs.

9. A folded cascode preamplifier, comprising:

an open-loop high frequency differential amplifier having differential inputs and differential current summing outputs, said open-loop differential amplifier having constant transconductance, and thus constant gain, over a large common mode input voltage range whereby at a low common mode input voltage when only PMOS transistors are active and at a high common mode input voltage when only NMOS transistors are active both said PMOS and said NMOS transistors have the same transconductance, and at a middle input common mode voltage, between said low and said high input voltage when both PMOS and NMOS transistors are active their transconductances are reduced such that their combined transconductance is equal to the individual transconductance of said PMOS and NMOS transistors, said open-loop high frequency differential amplifier further comprising;

at least a PMOS differential input pair of transistors, where the gates of said PMOS differential input pair are coupled to said differential inputs, respectively, the sources of said PMOS differential input pair coupled together and having a common tail current in series with a resistive means coupled to a positive power supply, and where the drains of said PMOS differential input pair are coupled to said differential summing outputs, respectively;

at least an NMOS differential input pair of transistors, where the gates of said NMOS differential input pair are coupled to said differential inputs, respectively, the sources of said NMOS differential input pair coupled together and having resistive means in series with a common tail current coupled to a negative power supply, and where the drains of said PMOS differential input pair are coupled via current sources to said differential summing outputs, respectively; and

an output stage coupled to said differential summing outputs and having differential outputs, said output stage comprising two cascoded current sources in parallel, where said differential summing outputs are coupled to the junction of said cascoded current sources, respectively.

10. The folded cascode preamplifier of claim 9, wherein said resistive means reduces the transconductance of said PMOS and said NMOS differential input pairs when both are active.

11. The folded cascode preamplifier of claim 9, wherein said PMOS and NMOS transistors are scaled such that the transconductance of said PMOS and NMOS transistors is the same when active.

12. The folded cascode preamplifier of claim 9, wherein said lower common mode input voltage ranges from said negative power supply up.

13. The folded cascode preamplifier of claim 9, wherein said upper common mode input voltage ranges from said positive power supply down.

14. The folded cascode preamplifier of claim 9, wherein the drains of said pair of PMOS transistors constitute said first and second summing point, respectively.

15. The folded cascode preamplifier of claim 9, wherein a current source is coupled between a positive power supply and the drains of said NMOS differential input pair, respectively.

16. The folded cascode preamplifier of claim 15, wherein current mirrors, controlled by said current sources, are coupled between said positive power supply and said differential summing outputs, respectively.

17. A folded cascode preamplifier, comprising:

an open-loop high frequency differential amplifier having differential inputs and differential current summing outputs, said open-loop differential amplifier having constant transconductance, and thus constant gain, over a large common mode input voltage range whereby at a low common mode input voltage when only PMOS transistors are active and at a high common mode input voltage when only NMOS transistors are active both said PMOS and said NMOS transistors have the same transconductance, and at a middle input common mode voltage, between said low and said high input voltage when both PMOS and NMOS transistors are active their transconductances are reduced such that their combined transconductance is equal to the individual transconductance of said PMOS and NMOS transistors, said open-loop high frequency differential amplifier further comprising;

a first and a second PMOS transistor together comprising a PMOS differential input pair, where the gates of said first and said second PMOS transistor are coupled to the first and second terminal of said differential inputs, respectively, the sources of said PMOS differential input pair coupled together and having a common tail current circuit in series with a first resistive means coupled to the terminal of a positive power supply, and where the drains of said first and said second PMOS transistor are coupled to first and second nodes of said differential summing outputs, respectively, to supply a summing current;

a first and a second NMOS transistor together comprising an NMOS differential input pair, where the gates of said first and said second NMOS transistor are coupled to said first and second terminal of said differential inputs, respectively, the sources of said NMOS differential input pair coupled together and having second resistive means in series with a common tail current circuit coupled to the terminal of a negative power supply, and where the drains of said first and said second NMOS transistor are coupled via a first and a second current source to the positive terminal of said power supply, respectively;

first and second current mirrors coupled to said positive power supply, their inputs coupled to the drains of said NMOS differential input pair, respectively, the outputs of said first and second current mirror coupled to said second and said first node of said differential summing outputs, respectively, said first and second current mirror supplying a summing current derived from said NMOS differential input pair; and

an output stage coupled to said differential summing outputs, said output stage producing an amplified signal at differential outputs, said output stage comprising a first cascoded current source in series with first resistive means coupled between the positive and a negative terminals of a power supply, and a second cascoded current source in series with second resistive means coupled between the positive and the negative terminals of said power supply, where said differential summing outputs are coupled to the junction of said first and said second cascoded current source, respectively, and where said differential outputs of said output stage are coupled between said first and said second resistive means and said first and said second cascoded current source, respectively.

18. The folded cascode preamplifier of claim 17, wherein said first and said second resistive means reduces the transconductance of said PMOS and said NMOS differential input pairs, respectively, when both are active.

19. The folded cascode preamplifier of claim 17, wherein said PMOS and NMOS transistors are scaled such that the transconductance of said PMOS and NMOS transistors is the same when active.

20. The folded cascode preamplifier of claim 17, wherein said lower common mode input voltage ranges from said negative power supply up.

21. The folded cascode preamplifier of claim 17, wherein said upper common mode input voltage ranges from said positive power supply down.

22. The folded cascode preamplifier of claim 17, wherein the PMOS and NMOS transistors of said PMOS and NMOS differential input pairs are scaled such that the transconductance of said PMOS and NMOS transistor is the same when active.

23. The folded cascode preamplifier of claim 17, wherein the PMOS and NMOS transistors of said output stage are scaled such that the transconductance of said PMOS and NMOS transistor is the same when active.

24. A folded cascode receiver preamplifier with CMOS a rail-to-rail input, comprising:

a differential amplifier with PMOS and NMOS transistor pairs coupled to differential inputs and receiving a common mode input voltage, where the drains of said PMOS and NMOS transistor pairs are in communication with a summing output; and

an output stage coupled to said summing output of said differential amplifier, said output stage with a pair of load transistor stages each comprising at least one PMOS and NMOS output transistor in parallel, said load transistor stages controlled by differential control means responding to the level of said common mode input voltage, where said PMOS and NMOS output transistors are activated by said differential control means in correspondence with said PMOS and NMOS transistor pairs, respectively.

25. The folded cascode receiver preamplifier of claim 24, wherein the ratio of the transconductance of said differential amplifier versus said output stage is constant, and were thereby the gain of said differential amplifier coupled to said output stage is constant, regardless of the common mode input voltage.

26. The folded cascode receiver preamplifier of claim 24, wherein, when active, the ratio of the transconductance of each of said PMOS transistor pairs to the transconductance of each of said PMOS output transistors is the same.

27. The folded cascode receiver preamplifier of claim 24, wherein, when active, the ratio of the transconductance of each of said NMOS transistor pairs to the transconductance of each of said NMOS output transistors is the same.

28. The folded cascode receiver preamplifier of claim 24, wherein, when active, the ratio of the sum of the transconductance of said PMOS and NMOS transistor pairs to the sum of the transconductance of said PMOS and NMOS output transistors is the same.

29. A folded cascode receiver preamplifier with a CMOS rail-to-rail input, comprising:

an open-loop high frequency differential amplifier having differential inputs and differential current summing outputs, where at a low common mode input voltage only PMOS transistors are active and at a high common mode input voltage only NMOS transistors are active, and where at a middle input common mode voltage, between said low and said high input voltage both PMOS and NMOS transistors are active, said open-loop high frequency differential amplifier further comprising;

a level shifting stage comprising a transistor pair, said level shifting stage coupled to said differential inputs, said level shifting stage shifting the level of said differential inputs;

at least a PMOS differential input pair of transistors, where the gates of said PMOS differential input pair are coupled to the outputs of said level shifting stage, the drains of said PMOS differential input pair in communication with said differential current summing outputs, and where the sources of said PMOS differential input pair are in communication with each other;

at least an NMOS differential input pair of transistors for current summing, where the gates of said NMOS differential input pair are coupled to said differential inputs, where the sources of said NMOS differential input pair are in communication with each other, and where the drains of said NMOS differential input pair are coupled to said differential current summing outputs;

an output stage coupled to said differential current summing outputs to amplify signals of said differential current summing outputs, said output stage comprising diode-connected PMOS and NMOS transistors as the load for the positive and negative outputs of said output stage; and

voltage sensing stages for low and high common mode input voltage sensing, said voltage sensing stages coupled to said output stage, said voltage sensing stage comprising switching means to activate said diode-connected PMOS transistors when said common mode input voltage is low and to activate said diode-connected NMOS transistors when said common mode input voltage is high.

30. The folded cascode receiver preamplifier of claim 29, wherein the ratio of the transconductance of said open-loop high frequency differential amplifier versus said output stage is constant, and were thereby the gain of said differential amplifier coupled to said output stage is constant, regardless of the common mode input voltage.

31. The folded cascode receiver preamplifier of claim 29, wherein the PMOS and NMOS transistors of said PMOS and NMOS differential input pairs are scaled such that the transconductance of said PMOS and NMOS transistor is the same when active.

32. The folded cascode receiver preamplifier of claim 29, wherein the PMOS and NMOS transistors of said output stage are scaled such that the transconductance of said PMOS and NMOS transistor is the same when active.

33. The folded cascode receiver preamplifier of claim 29, wherein said differential current summing outputs sum the currents of said PMOS and NMOS differential input pairs.

34. The folded cascode receiver preamplifier of claim 29, wherein said low common mode input voltage ranges from said negative power supply up.

35. The folded cascode receiver preamplifier of claim 29, wherein said high common mode input voltage ranges from said positive power supply down.

36. A folded cascode receiver preamplifier with a CMOS rail-to-rail input, comprising:

an open-loop high frequency differential amplifier having differential inputs and differential current summing outputs, said open-loop differential amplifier receiving at said differential inputs a common mode input voltage, where at a low common mode input voltage only PMOS transistors are active and at a high common mode input voltage only NMOS transistors are active, and where at a middle input common mode voltage, between said low and said high input voltage both PMOS and NMOS transistors are active, said open-loop high frequency differential amplifier further comprising;

a level shifting stage comprising a transistor pair, said level shifting stage coupled to said differential inputs, said level shifting stage shifting the voltage level of said differential inputs;

at least a PMOS differential input pair of transistors, where the gates of said PMOS differential input pair are coupled to the outputs of said level shifting stage, the drains of said PMOS differential input pair in communication with said differential current summing outputs, and where the sources of said PMOS differential input pair are coupled via resistive means with each other to improve the linearity of said PMOS differential input pair;

at least an NMOS differential input pair of transistors for current summing, where the gates of said NMOS differential input pair are coupled to said differential inputs, where the sources of said NMOS differential input pair are coupled via resistive means with each other to improve the linearity of said NMOS differential input pair, and where the drains of said NMOS differential input pair are coupled to said differential current summing outputs;

a low voltage sensing stage comprising a differential input pair for performing low common mode input voltage sensing when said common mode input voltage is low, where the gates of said differential input pair of said first voltage sensing stage are coupled to the outputs of said level shifting stage;

a high voltage sensing stage comprising a differential input pair for performing high common mode input voltage sensing when said common mode input voltage is high, where the gates of said differential input pair of said first voltage sensing stage are coupled to said differential inputs; and

an output stage coupled to said differential current summing outputs and providing an amplified output, said output stage having a negative and a positive load transistor stage, each comprising diode-connected PMOS and NMOS transistors coupled in parallel as the load for the negative and positive outputs of said output stage, respectively, and where outputs of said low and high voltage sensing stage couple to gates of control transistors in series with said diode-connected PMOS and NMOS transistors, respectively, of said negative and positive load transistor stage, whereby said voltage sensing stages activate said diode-connected PMOS and NMOS transistors of said negative and positive load transistor stage in correspondence with said PMOS and NMOS differential input pair of transistors.

37. The folded cascode receiver preamplifier of claim 36, wherein the ratio of the transconductance of said open-loop high frequency differential amplifier versus said output stage is constant, and were thereby the gain of said differential amplifier coupled to said output stage is constant, regardless of said common mode input voltage.

38. The folded cascode receiver preamplifier of claim 36, wherein said differential current summing outputs are summing the currents of said PMOS and NMOS differential input pairs.

39. The folded cascode receiver preamplifier of claim 36, wherein, when active, the ratio of the transconductance of each of said PMOS transistor pairs to the transconductance of each of said diode-connected PMOS transistors is the same.

40. The folded cascode receiver preamplifier of claim 36, wherein, when active, the ratio of the transconductance of each of said NMOS transistor pairs to the transconductance of each of said diode-connected NMOS transistors is the same.

41. The folded cascode receiver preamplifier of claim 36, wherein, when active, the ratio of the sum of the transconductance of said PMOS and NMOS transistor pairs to the sum of the transconductance of said diode-connected PMOS and NMOS transistors is the same.

42. The folded cascode receiver preamplifier of claim 36, wherein said summing currents of said PMOS differential input pair are generated by coupling the drains of said PMOS differential input pair to gates of a transistors pair and the drains of said transistor pair to said differential current summing outputs, respectively.

43. The folded cascode receiver preamplifier of claim 36, wherein said low common mode input voltage ranges from said negative power supply up.

44. The folded cascode receiver preamplifier of claim 36, wherein said high common mode input voltage ranges from said positive power supply down.

45. The folded cascode receiver preamplifier of claim 36, wherein PMOS and NMOS transistors of said output stage are scaled such that the transconductance of said PMOS and NMOS transistor is the same when active.

46. The folded cascode receiver preamplifier of claim 36, wherein said PMOS differential input pair of transistors operate in the saturation region when said common mode input voltage is low.

47. The folded cascode receiver preamplifier of claim 36, wherein the inputs to said low voltage sensing stage are coupled to the outputs of said level shifting stage.

48. The folded cascode receiver preamplifier of claim 36, wherein the inputs to said high voltage sensing stage are coupled to said differential inputs.

49. The method of maintaining a constant voltage gain over a large common mode input voltage range for a high frequency receiver preamplifier with rail-to-rail capability, comprising the steps of:

a) providing an open-loop differential preamplifier where PMOS and NMOS input transistor pairs are scaled to have the same transconductance;

b) inserting resistive means into the tail current paths of each of said PMOS and NMOS input transistor pairs thereby forcing current sources in their tail current paths into the triode region of operation;

c) reducing thereby the total transconductance of both said PMOS and NMOS input transistor pairs, when active, to that of one active input transistor pair;

d) keeping thereby the transconductance of said open-loop differential preamplifier constant regardless of the common mode input voltage; and

e) coupling current summing outputs to the drains of said PMOS and NMOS transistor pair.

50. The method of maintaining a constant voltage gain over a large common mode input voltage range for a high frequency receiver preamplifier with rail-to-rail capability, comprising the steps of:

a) providing an open-loop differential preamplifier with PMOS and NMOS input transistor pairs and differential current summing outputs;

b) coupling an output stage to said differential current summing outputs;

c) activating PMOS and NMOS output transistors of said output stage via control means in correspondence with said PMOS and NMOS input transistor pairs; and

d) keeping constant the ratio of the transconductance of said PMOS and NMOS output transistors divided by the transconductance of said PMOS and NMOS input transistor pairs.

51. The method of claim 50, wherein resistive means coupled between the sources of said PMOS and NMOS input transistors pairs, respectively, improve the linearity of the transconductance of said PMOS and NMOS input transistors pairs.