Triple cascode power amplifier of inner parallel configuration with dynamic gate bias technique
First Claim
1. A power amplifier, comprising:
- a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage;
a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal from the second transistor to the output end after re-amplification; and
a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain node of the third transistor, and a ground in series, and provides the dynamic gate bias to a gate of the third transistor by distributing an output signal at the drain of the third transistor through the first and second capacitors.
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Accused Products
Abstract
Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.
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Citations
27 Claims
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1. A power amplifier, comprising:
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a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage;
a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal from the second transistor to the output end after re-amplification; and
a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain node of the third transistor, and a ground in series, and provides the dynamic gate bias to a gate of the third transistor by distributing an output signal at the drain of the third transistor through the first and second capacitors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A power amplifier, comprising:
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an amplifying block with N transistors connected in parallel to receive and amplify an input signal individually;
a switching block that forms a cascode configuration by being connected to the amplifying block in series and that N transistors serially connected to each transistor in the amplifying block are connected in parallel;
a dynamic bias transistor that is operated by a dynamic gate bias by being connected in series between the switching block and an output end, and that reamplifies and outputs a signal coming from the switching block to the output end; and
a voltage dividing block that includes first and second capacitors connected in series between the output end and an ground, and that allots output signals through the first and second capacitors and provides the dynamic gate bias to a gate of the dynamic bias transistor. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification