High-voltage CMOS-compatible capacitors

• US 20060120013A1
• Filed: 01/04/2006
• Published: 06/08/2006
• Est. Priority Date: 08/05/2003
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Impinj, Inc.
• Inventors: Diorio, Christopher J., Bernard, Frederic J.
• Granted Patent: US 7,262,092 B2
• Time in Patent Office: Days
• US Class Current: 361/301.400
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 27/0811 MIS diodes
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence

Abstract

A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate having a first semiconductive body and a second plate having a floating electrode. The first and second semiconductive bodies are electrically isolated from each other. The floating electrode includes an intercapacitor node configured to self-adjust to a value less than a working voltage impressed on the stacked capacitor.

Claims

1. A process for charging a floating electrode of a stacked capacitor, comprising:

coupling a first potential to a first electrode of the stacked capacitor, the first electrode being coupled to a first semiconductive body;

coupling a second potential to a second electrode of the stacked capacitor, the second electrode being coupled to a second semiconductive body that is electrically isolated from the first semiconductive body, a difference between the first and second potentials comprising a working voltage of the stacked capacitor; and

charging a floating electrode to a floating voltage whose value is less than the working voltage, wherein the floating electrode is capacitively coupled to the first and second semiconductive bodies and includes an intercapacitor node.

2. The process of claim 1, further comprising storing the floating voltage on the floating electrode following removal of the first and second potentials from the stacked capacitor.

3. The process of claim 1, wherein the act of charging comprises tunneling charge carriers through a dielectric, wherein the dielectric includes a first portion disposed between the first semiconductive body and a corresponding portion of the floating electrode and the dielectric includes a second portion disposed between the second semiconductive body and a corresponding portion of the floating electrode.

4. The process of claim 1, wherein the acts of coupling first and second potentials comprise coupling the first and second potentials to first and second electrodes of the stacked capacitor, and wherein the stacked capacitor comprises a plurality of PFETs, NFETs or MOSCAPs, or any combination thereof coupled to the common intercapacitor node.

5-15. -15. (canceled)

16. A process for forming a stacked floating-gate capacitor, comprising:

forming a first semiconductive body;

forming a second semiconductive body that is electrically isolated from the first semiconductive body;

disposing a tunneling dielectric atop at least a portion of each of the first and second semiconductive bodies; and

creating a floating gate at least partly disposed over the tunneling dielectric and the first and second semiconductive bodies.

17. The process of claim 16, wherein creating includes creating an intercapacitor node as a portion of the floating gate.

18. The process of claim 16, wherein forming the first and second semiconductive bodies comprises doping a semiconductive substrate.

19. The process of claim 16, wherein forming the first and second semiconductive bodies comprises forming doped tubs in a silicon substrate.

20. The process of claim 16, wherein creating comprises creating a polycrystalline silicon floating gate.

21. The process of claim 16, wherein disposing comprises disposing a dielectric layer having a thickness of between three and seven nanometers.

22. The process of claim 16, wherein forming at least one of the first and second semiconductive bodies comprises forming at least one PMOS-type semiconductive body.

23. The process of claim 16, wherein forming at least one of the first and second semiconductive bodies comprises forming at least one n-well.

24. The process of claim 16, wherein creating includes creating an intercapacitor node as a portion of the floating gate, and further comprising forming a transistor having a power electrode coupled to the intercapacitor node.

25. The process of claim 16, wherein creating includes creating an intercapacitor node as a portion of the floating gate, and further comprising forming a first transistor having a power electrode coupled to the intercapacitor node and forming a second transistor having a power electrode coupled to the intercapacitor node.

26. The process of claim 16, wherein creating a floating gate comprises creating a floating gate configured to self-adjust to about one-half of a working voltage impressed on the stacked floating-gate capacitor.