Memory cell array

• US 20060120129A1
• Filed: 12/07/2004
• Published: 06/08/2006
• Est. Priority Date: 12/07/2004
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Schloesser, Till
• Granted Patent: US 7,139,184 B2
• Time in Patent Office: Days
• US Class Current: 365/53
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first direction, and continuous active area lines, wherein transistors are at least partially formed in the active area lines. The transistors electrically couple corresponding memory cells to corresponding bit lines via bit line contacts, and the transistors are addressed by the word lines. The bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line. Neighboring bit line contacts which are connected with one active area line are connected with neighboring bit lines. Consequently, one active area line is crossed by a plurality of bit lines.

Claims

1. A memory cell array comprising:

memory cells, each of the memory cells comprising a storage element and an access transistor;

bit lines running along a first direction;

word lines running along a second direction substantially perpendicular to the first direction; and

a semiconductor substrate, continuous active area lines and isolation trenches being formed in the semiconductor substrate, the isolation trenches being adjacent to the active area lines, and the isolation trenches being adapted to electrically isolate neighboring active area lines from each other, the access transistors being at least partially formed in the active area lines and electrically coupling corresponding storage elements to corresponding bit lines via bit line contacts, the transistors being addressed by the word lines;

wherein the bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line; and

wherein neighboring bit line contacts, each of which is connected to an active area line, are connected with neighboring bit lines.

2. The memory cell array according to claim 1, wherein the active area lines are formed as straight lines.

3. The memory cell array according claim 1, wherein each of the storage elements comprises a storage capacitor.

4. The memory cell array according to claim 3, wherein the storage capacitor is a stacked capacitor.

5. The memory cell array according to claim 1, wherein an angle between the active area lines and the bit lines is between approximately 10°

to 60°

.

6. The memory cell array according to claim 5, wherein an angle between the active area lines and the bit lines is between approximately 10°

to 25°

.

7. The memory cell array according to claim 6, wherein an angle between the active area lines and the bit lines is between approximately 18°

to 19°

.

8. The memory cell array according to claim 1, wherein one bit line contact is associated with two neighboring transistors that are formed in one active area line.

9. The memory cell array according to claim 1, further comprising isolation gate lines which are adapted to isolate neighboring transistors from each other, the isolation gate lines being arranged in parallel with the word lines.

10. The memory cell array according to claim 9, wherein two word lines are followed by one isolation gate line, and one isolation gate line is followed by two word lines.

11. A memory cell array comprising:

memory cells, each of the memory cells comprising a storage element and an access transistor;

bit lines running along a first direction, the bit lines being formed as straight bit lines; and

a semiconductor substrate, continuous active area lines and isolation trenches being formed in the semiconductor substrate, the isolation trenches being adjacent to the active area lines, and the isolation trenches being adapted to electrically isolate neighboring active area lines from each other, the access transistors being at least partially formed in the active area lines and electrically coupling corresponding storage elements to corresponding bit lines via bit line contacts, the access transistors being addressed by the word lines;

wherein the bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line; and

wherein neighboring bit line contacts, each of which is connected with an active area line, are connected with neighboring bit lines.

12. The memory cell array according to claim 11, further comprising a plurality of word lines running along a second direction intersecting the first direction, the access transistors being addressed by the word lines.

13. The memory cell array according claim 11, wherein each of the storage elements comprises a storage capacitor.

14. The memory cell array according to claim 13, wherein the storage capacitor is a stacked capacitor.

15. The memory cell array according to claim 11, wherein an angle between the active area lines and the bit lines is between approximately 10°

to 60°

.

16. The memory cell array according to claim 15, wherein an angle between the active area lines and the bit lines is between approximately 10°

to 25°

.

17. The memory cell array according to claim 16, wherein an angle between the active area lines and the bit lines is between approximately 18°

to 19°

.

18. The memory cell array according to claim 11, wherein one bit line contact is associated with two neighboring transistors that are formed in one active area line.

19. The memory cell array according to claim 12, further comprising isolation gate lines which are adapted to isolate neighboring transistors from each other, the isolation gate lines being arranged in parallel with the word lines.

20. The memory cell array according to claim 19, wherein two word lines are followed by one isolation gate line, and one isolation gate line is followed by two word lines.

21. The memory cell array according to claim 11, wherein the active area lines are formed as straight lines.