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Logic synthesis of multi-level domino asynchronous pipelines

  • US 20060120189A1
  • Filed: 11/10/2005
  • Published: 06/08/2006
  • Est. Priority Date: 11/22/2004
  • Status: Active Grant
First Claim
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1. A computer-implemented method for optimizing a circuit design, comprising:

  • generating a gate level circuit description corresponding to the circuit design, the gate level circuit description comprising a plurality of pipelines across a plurality of levels; and

    using a linear programming technique, adding a first number of buffers to selected stages of the pipelines such that the pipelines are balanced, at least one performance constraint is satisfied, and an objective function characterizing the circuit design is minimized.

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