Bidirectional communication control apparatus, terminal apparatus, and bidirectional communication control method

• US 20060120400A1
• Filed: 01/06/2006
• Published: 06/08/2006
• Est. Priority Date: 07/11/2003
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ishii, Tatsuji, Fukuoka, Toshihiko, Kumazawa, Machiya
• Granted Patent: US 7,580,358 B2
• Time in Patent Office: Days
• US Class Current: 370/447
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 65/1101 Session protocols

Abstract

A terminal apparatus of a communication system is provided with an MAC section (bidirectional communication apparatus), a PHY section, a tuner, and a back-end section. The MAC section comprises a downstream data processing block having a function of substituting for a portion of the process of the CPU, a upstream data processing block having a function of substituting for a portion of the process of the CPU, a bus data arbitration processing block, a CPU bus, the CPU, and a storage apparatus. The downstream data processing block and the upstream data processing block perform direct data transmission/reception while bypassing the CPU bus.

Claims

1. A bidirectional communication control apparatus which is provided in a terminal apparatus which performs bidirectional data transmission/reception with respect to a center apparatus, the bidirectional communication control apparatus comprising:

a CPU;

a first storage apparatus;

a CPU bus connecting between the CPU and the first storage apparatus;

a downstream data processing block of receiving downstream data transmitted from the center apparatus to the terminal apparatus, and performing data processing;

an upstream data processing block of performing data processing to generate upstream data to be transmitted from the terminal apparatus to the center apparatus; and

a bus data arbitration processing block of regulating a flow of data on the CPU bus, the bus data arbitration processing block being connected to the CPU bus, the downstream data processing block, and the upstream data processing block,

wherein the downstream data processing block and the upstream data processing block perform direct data transmission/reception with respect to each other.

2. The bidirectional communication control apparatus of claim 1, further comprising:

a data processor having a register of temporarily holding data, the data processor being connected to the CPU bus, the upstream data processing block, and the downstream data processing block while bypassing the bus data arbitration processing block.

3. The bidirectional communication control apparatus of claim 1, further comprising:

a second storage apparatus of storing a portion of contents stored in the first storage apparatus instead of the first storage apparatus, the second storage apparatus being connected to the CPU bus, the upstream data processing block, and the downstream data processing block while bypassing the bus data arbitration processing block.

4. The bidirectional communication control apparatus of claim 1, further comprising:

a second storage apparatus of storing a portion of contents stored in the first storage apparatus instead of the first storage apparatus, the second storage apparatus being connected to the upstream data processing block, the downstream data processing block, and the first storage apparatus while bypassing the bus data arbitration processing block and the CPU bus.

5. The bidirectional communication control apparatus of claim 4, further comprising:

a third storage apparatus having a function of temporarily storing data, the third storage apparatus being connected to the upstream data processing block, the downstream data processing block, and the second storage apparatus.

6. The bidirectional communication control apparatus of claim 1, further comprising:

a data processor having a register of temporarily holding data, the data processor being connected to the CPU bus, the upstream data processing block, and the downstream data processing block while bypassing the bus data arbitration processing block;

a second storage apparatus of storing a portion of contents stored in the first storage apparatus instead of the first storage apparatus, the second storage apparatus being connected to the upstream data processing block, the downstream data processing block, and the CPU bus while bypassing the bus data arbitration processing block;

a third storage apparatus having a function of temporarily storing data, the third storage apparatus being connected to the upstream data processing block, the downstream data processing block, and the second storage apparatus; and

a control block of controlling output/input of data with respect to the second storage apparatus and the third storage apparatus, the control block being connected to the upstream data processing block, the downstream data processing block, the second storage apparatus, the third storage apparatus, and the data processor.

7. The bidirectional communication control apparatus of claim 1, further comprising:

a data processor having a register of temporarily holding data, the data processor being connected to the CPU bus, the upstream data processing block, and the downstream data processing block while bypassing the bus data arbitration processing block;

a second storage apparatus of storing a portion of contents stored in the first storage apparatus instead of the first storage apparatus, the second storage apparatus being connected to the upstream data processing block, the downstream data processing block, and the first storage apparatus while bypassing the bus data arbitration processing block and the CPU bus;

a third storage apparatus having a function of temporarily storing data, the third storage apparatus being connected to the upstream data processing block, the downstream data processing block, and the second storage apparatus; and

a control block of controlling output/input of data with respect to the second storage apparatus and the third storage apparatus, the control block being connected to the upstream data processing block, the downstream data processing block, the second storage apparatus, the third storage apparatus, and the data processor.

8. The bidirectional communication control apparatus of claim 1, wherein the downstream data processing block has a basic process circuit of performing syntax analysis, header analysis, and data format conversion with respect to the downstream data, and

the basic process circuit performs direct data transmission/reception with respect to the upstream data processing block.

9. The bidirectional communication control apparatus of claim 1, wherein the upstream data processing block has a concatenated frame header adding process circuit of concatenating a plurality of pieces of upstream data into a single piece of data, and adding a concatenated frame header to the single piece of concatenated data, and

the concatenated frame header adding process circuit performs direct data transmission/reception with respect to the downstream data processing block.

10. The bidirectional communication control apparatus of claim 1, wherein the upstream data processing block has a divided frame header adding process circuit of dividing a single piece of upstream data into a plurality of portions, and adding a divided frame header to each of the plurality of portions, and

the divided frame header adding process circuit performs direct data transmission/reception with respect to the downstream data processing block.

11. A terminal apparatus of performing bidirectional data transmission/reception with respect to a center apparatus, comprising:

a tuner of receiving an RF signal transmitted from the center apparatus and converting the RF signal into an IF signal;

a downstream PHY block of receiving the IF signal and extracting the downstream data;

an upstream PHY block of demodulating the upstream data output from the upstream data processing block and transmitting the demodulated upstream data as an RF signal to the center apparatus; and

a bidirectional communication control apparatus for controlling transmission/reception of data transmitted/received between the center apparatus and the terminal apparatus,

wherein the bidirectional communication control apparatus comprises;

a CPU;

a first storage apparatus;

a CPU bus connecting between the CPU and the first storage apparatus;

a downstream data processing block of receiving downstream data transmitted from the center apparatus to the terminal apparatus, and performing data processing;

an upstream data processing block of performing data processing to generate upstream data to be transmitted from the terminal apparatus to the center apparatus; and

a bus data arbitration processing block of regulating a flow of data on the CPU bus, the bus data arbitration processing block being connected to the CPU bus, the downstream data processing block, and the upstream data processing block,

wherein the downstream data processing block and the upstream data processing block perform direct data transmission/reception with respect to each other.

12. The terminal apparatus of claim 11, further comprising:

a back-end section having a function of performing at least an image process, the back-end section being connected to the CPU bus.

13. A bidirectional communication control method for use in a terminal apparatus of performing bidirectional data transmission/reception with respect to a center apparatus, comprising:

a step (a) of receiving downstream data transmitted from the center apparatus to the terminal apparatus, and performing a downstream data process;

a step (b) of performing an upstream data process to generate upstream data to be transmitted from the terminal apparatus to the center apparatus; and

a step (c) of storing at least a portion of process contents of steps (a) and (b) in a storage apparatus,

wherein steps (a) and (b) include performing the downstream data process and the upstream data process with reference to the process contents of each other stored in the storage apparatus.

14. The method of claim 13, wherein step (a) includes a basic process of performing syntax analysis, header analysis, and data format conversion with respect to the downstream data;

and

the basic process is performed with reference to the process contents of the upstream data process.

15. The method of claim 13, wherein step (b) includes a concatenated frame header adding process of concatenating a plurality of pieces of upstream data into a single piece of data, and adding a concatenated frame header to the single piece of concatenated data, and

the concatenated frame header adding process is performed with reference to the process contents of the upstream data process.

16. The method of claim 13, wherein step (b) includes a divided frame header adding process of dividing a single piece of upstream data into a plurality of portions and adding a divided frame header to each of the plurality of divided portions, and

the divided frame header adding process is performed with reference to the process contents of the downstream data process.