Calibrated data communication system and method

• US 20060120409A1
• Filed: 01/05/2006
• Published: 06/08/2006
• Est. Priority Date: 10/19/1999
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Sidiropoulos, Stefanos, Kim, Jun, Stark, Donald C., Garlepp, Bruno W., Horowitz, Mark A., Donnelly, Kevin S., Yu, Leung, Lau, Benedict Chung-Kwong, Vu, Roxanne, Zerbe, Jared LeVan, Ho, Tsyr-Chyang
• Granted Patent: US 7,535,933 B2
• Time in Patent Office: Days
• US Class Current: 370/516
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

Claims

1. A system comprising:

a memory device including;

a receiver to sample a data sequence, the receiver to provide receiver data from sampling the data sequence; and

a transmitter to output the receiver data; and

a controller device coupled to the memory device, the controller device including;

a transmitter to output the data sequence to the memory device;

a receiver to receive the receiver data; and

a register to store information representative of a timing offset to apply to data output by the transmitter of the controller device, wherein the timing offset is determined based on the data sequence and the receiver data.

2. The system of claim 1, further comprising:

a control line coupled to the controller device and the memory device; and

a termination resistor coupled to the control line such that a control signal, transmitted by the memory controller onto the control line, propagates past the memory device before reaching the termination resistor.

3. The system of claim 1, further comprising:

a locked loop circuit on the controller device, the locked loop circuit to generate a transmit clock signal, wherein the transmitter of the controller device outputs the data sequence in response to the transmit clock signal; and

a signal line to carry a reference clock signal from the controller device to the memory device wherein the receiver data indicates phase information of the data sequence relative to a phase of the reference clock signal used to sample data at the memory device.

4. The system of claim 1, wherein the timing offset is determined during a calibration phase of system operation.

5. The system of claim 1, wherein the timing offset is determined periodically during system operation.

6. The system of claim 1, wherein the timing offset is determined upon detection of a threshold number of bit errors.

7. The system of claim 1, wherein the receiver data is stored in the memory device after being sampled by the receiver of the memory device and before being output by the transmitter of the memory device.

8. The system of claim 1, wherein the data sequence includes a predetermined number of signaling transitions.

9. A controller device comprising:

a transmitter to output a data sequence to a memory device that samples the data sequence and provides receiver data from sampling the data sequence;

a receiver to receive the receiver data from the memory device; and

a register to store a value representative of a timing offset to apply to data output by the transmitter, wherein the timing offset is determined based on the data sequence and the receiver data.

10. The controller device of claim 9, further comprising a register to store a value representative of a timing offset to apply to a data sampling instant of the receiver.

11. The controller device of claim 9, further comprising a locked loop circuit to generate a clock signal such that the data sequence is output in response to the clock signal.

12. A controller device comprising:

a transmitter to output a first data sequence to a first memory device that samples the first data sequence and provides first receiver data from sampling the data sequence, the transmitter to output a second data sequence to a second memory device that samples the second data sequence and provides second receiver data from sampling the second data sequence;

a receiver to receive the first receiver data from the first memory device and a second data sequence from the second memory device;

a first register to store a value representative of a first timing offset to apply to data output to the first memory device, wherein the first timing offset is determined based on the first data sequence and the first receiver data; and

a second register to store a value representative of a second timing offset to apply to data output to the second memory device, wherein the second timing offset is determined based on the second data sequence and the second receiver data.

13. A method of operation in a memory system that includes a controller device coupled to a memory device, the method comprising:

transmitting a data sequence from the controller device to the memory device;

sampling the data sequence at the memory device to provide receiver data from the sampling of the data sequence;

transmitting the receiver data from the memory device to the controller device; and

generating a value representative of a timing offset to apply to data output by a transmitter of the controller device, wherein the timing offset is determined based on a difference between the data sequence and the receiver data.

14. The method of claim 13, wherein generating the value is performed during a calibration phase of system operation.

15. The method of claim 13, wherein generating the value is performed periodically during system operation.

16. The method of claim 13, wherein generating the value is performed upon detection of a threshold number of bit errors.

17. A system comprising:

a controller device including a transmitter to output a data sequence; and

a memory device including;

a receiver to sample the data sequence, the receiver to provide receiver data from sampling the data sequence; and

a register to store information representative of a sampling timing offset to apply to a sampling of data being sampled by the receiver, wherein the timing offset is determined based on the data sequence and the receiver data.

18. The system of claim 17, further comprising:

a control line coupled to the controller device and the memory device; and

a termination resistor coupled to the control line such that a control signal, transmitted by the memory controller onto the control line, propagates past the memory device before reaching the termination resistor.

19. The system of claim 17, wherein the memory device includes a transmitter to output the receiver data to the controller device, and wherein the controller device includes a receiver to receive the receiver data from the memory device, wherein the controller device determines the information representative of the sampling timing offset based on a difference between the receiver data and the data sequence.

20. The system of claim 17, wherein the controller further includes a locked loop circuit to sweep the phase of a clock signal across a predetermined phase range, wherein the clock signal is used to transmit the data sequence to the memory device.

21. A system comprising:

a first memory device and a second memory device; and

a controller device including;

a transmitter to output a first data sequence to the first memory device and a second data sequence to the second memory device

a receiver to receive first receiver data from the first memory device and second receiver data from the second memory device;

a first register to store information representative of a first timing offset to apply to data to be transmitted to the first memory device, wherein the first timing offset is determined based on the first data sequence and first receiver data, wherein the first receiver data is based on the first memory device sampling the first data sequence; and

a second register to store information representative of a second timing offset to apply to data to be transmitted to the second memory device, wherein the second timing offset is determined based on the second data sequence and the second receiver data, wherein the second receiver data is based on the second memory device sampling the second data sequence;

a control line coupled to the controller device, the first memory device, and the second memory device; and

a termination resistor coupled to the control line such that a control signal, transmitted by the memory controller on the control line, propagates past the first and second memory devices before reaching the termination resistor.

22. A system comprising:

a first memory device having a receiver to sample a plurality of data bits; and

a controller device including;

a transmitter to output the plurality of data bits to the first memory device; and

a first register to store information representative of a first timing offset to apply to data to be transmitted to the first memory device, wherein the first timing offset is determined based on information derived from the plurality of data bits sampled by the receiver of the first memory device;

a control line coupled to the controller device and the first memory device; and

a termination resistor coupled to the control line such that a control signal, transmitted by the memory controller on the control line, propagates past the first memory device before reaching the termination resistor.

23. The system of claim 22, further comprising a second memory device coupled to the control line, wherein the control signal propagates past the second memory device before reaching the termination resistor, the second memory device having a receiver to sample a second plurality of data bits.

24. The system of claim 23, further comprising a second register disposed on the controller device to store information representative of a second timing offset to apply to data to be transmitted to the second memory device, wherein the second timing offset is determined based on information derived from the second plurality of data bits sampled by the receiver of the second memory device.