Shallow trench filled with two or more dielectrics for isolation and coupling for stress control

• US 20060121394A1
• Filed: 01/26/2006
• Published: 06/08/2006
• Est. Priority Date: 10/01/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chi, Min-Hwa
• Granted Patent: US 7,320,926 B2
• Time in Patent Office: Days
• US Class Current: 430/314
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and filling said trenches. The first layer is planarized to the stop layer leaving the first layer within the trenches. The first layer is removed from a subset of the trenches. A second layer is deposited over the stop layer and within the subset of trenches and planarized to the stop layer leaving the second layer within the subset of trenches to complete fabrication of shallow trenches having different trench fill materials. The trench fill materials may be dielectric layers having different dielectric constants or they may be a dielectric layer and a conducting layer. The method can be extended to provide three or more different trench fill materials.

Claims

1-20. -20. (canceled)

21. A method for fabricating a n+ to n+ capacitor, comprising:

providing a stop layer on a substrate;

etching a plurality of trenches through said stop layer and into said substrate;

depositing a first layer over said stop layer and filling said trenches wherein said first layer comprises a dielectric material having a first dielectric constant;

planarizing said first layer to said stop layer leaving said first layer within said trenches;

thereafter removing said first layer from a subset of said trenches;

depositing a second layer over said stop layer and within said subset of trenches, wherein said second layer comprises a dielectric material having a second dielectric constant higher than said first dielectric constant;

planarizing said second layer to said stop layer leaving said second layer within said subset of trenches; and

forming n+ junctions on either side of one of said subset of trenches, wherein said one of said subset of trenches forms a capacitor dielectric of said n+ to n+ capacitor.

22. The method according to claim 21 wherein said second dielectric constant is greater than about 7.0.

23. A method for fabricating a p+ to p+ capacitor, comprising:

forming an n-well within said substrate;

providing a stop layer on a substrate;

etching a plurality of trenches through said slop layer and into said substrate;

depositing a first layer over said stop layer and filling said trenches, wherein said first layer comprises a dielectric material having a first dielectric constant;

planarizing said first layer to said stop layer leaving said first layer within said trenches;

thereafter removing said first layer from a subset of said trenches;

depositing a second layer over said stop layer and within said subset of trenches, wherein said second layer comprises a dielectric material having a second dielectric constant higher than said first dielectric constant;

planarizing said second layer to said slop layer leaving said second layer within said subset of trenches; and

forming p+ junctions within said n-well on either side of one of said subset of trenches, wherein said one of said trenches forms a capacitor dielectric for said p+ to p+ capacitor.

24. The method according to claim 23 wherein said second dielectric constant is greater than about 7.0.

25. A method for fabricating a vertical MOSFET, comprising:

forming a deep n-well within said substrate;

providing a stop layer on a substrate;

etching a plurality of trenches through said stop layer and into said substrate;

depositing a first layer over said stop layer and filling said trenches, wherein said first layer comprises a dielectric material having a first dielectric constant;

planarizing said first layer to said stop layer leaving said first layer within said trenches;

thereafter removing said first layer one a subset of said trenches;

depositing a second layer over said stop layer and within said subset of trenches, wherein said second layer comprises a dielectric material having a second dielectric constant higher than said first dielectric constant;

planarizing said second layer to said stop layer leaving said second layer within said subset of trenches;

forming within said deep n-well a first n+ junction on one side of one of said subset of trenches, called a high-k trench, and forming a p-well underlying said first n+ junction, wherein said p-well forms the body of a vertical MOSFET device; and

forming within said deep n-well a second gate n+ junction on another side of said high-k trench, wherein said second n+ junction is formed deeper than said first n+ junction and wherein a p-base is formed underlying said second n+ junction;

wherein said vertical MOSFET device is turned on by forming an inversion layer at a sidewall of said body adjacent to said high-k trench.

26. A method for fabricating a vertical MOSFET, comprising:

providing a stop layer on a substrate;

etching a plurality of trenches through said stop layer and into said substrate;

depositing a first layer over said stop layer and filling said trenches, wherein said first layer comprises a dielectric material having a first dielectric constant;

planarizing said first layer to said stop layer leaving said first layer within said trenches;

thereafter removing said first layer form a subset of said trenches;

depositing a second layer over said stop layer and within said subset of trenches, wherein said second layer comprises a dielectric material having a second dielectric constant higher than said first dielectric constant;

planarizing said second layer to said slop layer leaving said second layer within said subset of trenches;

forming a first p+ junction on one side of one of said trenches filled with said one of said first and second layers having said higher dielectric constant, called a high-k trench, and forming a n-well underlying said p+ junction, wherein said n-well forms the body of a vertical MOSFET device; and

forming a second gate p+ junction on another side of said high-k trench, wherein said second n+ junction is formed deeper than said first p+ junction and a n-base is formed underlying said second p+ junction;

wherein said vertical MOSFET device is turned on by forming an inversion layer at a sidewall of said body adjacent to said high-k trench.

27-28. -28. (canceled)

29. A method for fabricating a semiconductor device, comprising:

providing a stop layer on a substrate;

etching two first trenches and one second trench between the first trenches through said stop layer and into said substrate;

forming a first layer in the first trenches wherein said first layer comprises a dielectric material having a first dielectric constant;

forming a second layer in the second trench, wherein said second layer comprises a dielectric material having a second dielectric constant higher than said first dielectric constant;

forming a first junction of a first conductivity type on one side of the second trench; and

forming a second junction of a first conductivity type on another side of the second trench.

30. The method according to claim 29, wherein the semiconductor device is a capacitor and the second trench forms a capacitor dielectric of the capacitor.

31. The method according to claim 30, wherein the first junction and the second junction are formed at the same time.

32. The method according to claim 30, further comprising forming a well of a second conductivity type opposing to the first conductivity type within said substrate prior to the formation of the stop layer.

33. The method according to claim 30, wherein the first conductivity type is n conductivity type and the junctions are formed with n+ concentrations.

34. The method according to claim 32, wherein the first conductivity type is p conductivity type and the second conductivity type is n conductivity type, and the junctions are formed within said well, having p+ concentrations.

35. The method according to claim 29, further comprising forming a body of a second conductivity type of a vertical MOSFET device underlying the first junction, and forming a base of the second conductivity type of the vertical MOSFET device underlying the second junction, and wherein the second junction is deeper than the first junction and the vertical MOSFET device is turned on by forming an inversion layer at a side wall of the body adjacent the second trench.

36. The method according to claim 35, further comprising forming a deep second well of said first conductivity type within said substrate prior to the formation of the stop layer.

37. The method according to claim 35, wherein the first conductivity type is p conductivity type and the first and second junctions are formed with p+ concentrations.

38. The method according to claim 36, wherein the first conductivity type is n conductivity type and the second conductivity type is p conductivity type, and the first and second junctions are formed within said well, having p+ concentrations.