Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors
First Claim
Patent Images
1. A method of forming memory circuitry comprising:
- providing a silicon-comprising substrate comprising a memory array area and a peripheral circuitry area, the memory array area comprising a first pair of spaced adjacent electrically conductive structures received over the silicon-comprising substrate in at least a first cross-section of the substrate, the peripheral circuitry area comprising a second pair of spaced adjacent electrically conductive structures received over the silicon-comprising substrate at least in a second cross-section of the substrate, the conductive structures of the second pair being spaced further from one another in the second cross-section than are those of the first pair in the first cross-section;
depositing a masking material between the conductive structures of each of the first and second pairs;
removing the masking material effective to expose silicon between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section;
after the removing effective to expose silicon, depositing metal over the substrate and annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section; and
after the annealing, removing at least some of the masking material from between the conductive structures of the first pair in the first cross-section.
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Abstract
The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.
50 Citations
82 Claims
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1. A method of forming memory circuitry comprising:
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providing a silicon-comprising substrate comprising a memory array area and a peripheral circuitry area, the memory array area comprising a first pair of spaced adjacent electrically conductive structures received over the silicon-comprising substrate in at least a first cross-section of the substrate, the peripheral circuitry area comprising a second pair of spaced adjacent electrically conductive structures received over the silicon-comprising substrate at least in a second cross-section of the substrate, the conductive structures of the second pair being spaced further from one another in the second cross-section than are those of the first pair in the first cross-section;
depositing a masking material between the conductive structures of each of the first and second pairs;
removing the masking material effective to expose silicon between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section;
after the removing effective to expose silicon, depositing metal over the substrate and annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section; and
after the annealing, removing at least some of the masking material from between the conductive structures of the first pair in the first cross-section. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of forming memory circuitry comprising:
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providing a silicon-comprising substrate comprising a memory array area and a peripheral circuitry area, the memory array area comprising a first pair of spaced adjacent electrically conductive structures received over the silicon-comprising substrate in at least a first cross-section of the substrate, the peripheral circuitry area comprising a second pair of spaced adjacent electrically conductive structures received over the silicon-comprising substrate in at least a second cross-section of the substrate, the conductive structures of the second pair being spaced further from one another in the second cross-section than are those of the first pair in the first cross-section;
depositing electrically conductive material between the conductive structures of each of the first and second pairs;
removing the conductive material effective to expose silicon between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section; and
after the removing, depositing metal over the substrate and annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A method of forming integrated circuitry comprising:
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providing a silicon-comprising substrate comprising a first circuitry area and a second circuitry area, the first circuitry area comprising a first pair of spaced adjacent gate electrodes received over the silicon-comprising substrate in at least a first cross-section of the substrate, spaced and facing anisotropically etched electrically insulative sidewall spacers being provided in the first cross-section between the gate electrodes of the first pair, the second circuitry area comprising a second pair of spaced adjacent gate electrodes received over the silicon-comprising substrate in at least a second cross-section of the substrate, spaced and facing anisotropically etched insulative sidewall spacers being provided in the second cross-section between the gate electrodes of the second pair, the facing anisotropically etched sidewall spacers between the second pair being spaced further from one another in the second cross-section than are those received between the first pair in the first cross-section;
depositing a masking material between the facing anisotropically etched sidewall spacers received between each of the first and second pairs of gate electrodes;
removing the masking material effective to expose silicon between the facing anisotropically etched sidewall spacers received between the second pair in the second cross-section but not between the facing anisotropically etched sidewall spacers received between the first pair in the first cross-section; and
after the removing, depositing metal over the substrate and annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide between the facing anisotropically etched sidewall spacers received between the second pair in the second cross-section but not between the facing anisotropically etched sidewall spacers received between the first pair in the first cross-section. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
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52. A method of forming integrated circuitry comprising:
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providing a silicon-comprising substrate comprising a first circuitry area and a second circuitry area, the first circuitry area comprising a first pair of spaced adjacent gate electrodes received over the silicon-comprising substrate in at least a first cross-section, the second circuitry area comprising a second pair of spaced adjacent gate electrodes received over the silicon-comprising substrate in at least a second cross-section, the gate electrodes of the second pair being spaced further from one another in the second cross-section than are those of the first pair in the first cross-section;
depositing a masking material between the gate electrodes of each of the first and second pairs;
removing the masking material effective to expose silicon between the gate electrodes of the second pair in the second cross-section but not between the gate electrodes of the first pair in the first cross-section, said removing being ineffective to expose conductive material of the gate electrodes in the first and second cross-sections; and
after the removing, depositing metal over the substrate and annealing the substrate effective to react the metal with silicon of the substrate to form a conductive metal silicide between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section, said depositing and annealing being ineffective to form silicide on the conductive material of the gate electrodes in the first and second cross-sections. - View Dependent Claims (53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70)
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71. A method of forming a field effect transistor, comprising:
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forming a gate electrode of a field effect transistor over a silicon comprising substrate, the gate electrode comprising a sidewall;
forming a first electrically insulative anisotropically etched sidewall spacer over the sidewall of the gate electrode;
forming a second anisotropically etched sidewall spacer over and distinct from the first sidewall spacer;
depositing metal over the first and second sidewall spacers and over silicon of a source/drain region of the transistor proximate the second sidewall spacer; and
annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide on the source/drain region which is spaced from the first sidewall spacer. - View Dependent Claims (72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82)
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Specification