Contact resistance reduction by new barrier stack process

• US 20060121724A1
• Filed: 12/02/2004
• Published: 06/08/2006
• Est. Priority Date: 12/02/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Grunow, Stephan, Leavy, Montray, Papa Rao, Satyavolu S., Russell, Noel M., Yue, Duofeng
• Granted Patent: US 7,256,121 B2
• Time in Patent Office: Days
• US Class Current: 438/625
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76862 Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence

Abstract

The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.

Claims

1. A method for forming an interconnect, comprising:

forming an opening in a dielectric layer, depositing a liner over an inner surface of the opening, the depositing forming a reentrant profile near a top portion of the opening; and

etching a portion of the liner, including removing at least a portion of the liner to reduce the reentrant profile and removing at least a portion of the liner at the bottom of the opening to expose an underlying layer located under the dielectric layer.

2. The method as recited in claim 1 wherein at least a portion of the liner located at the reentrant profile is deposited at the bottom of the opening.

5. The method as recited in claim 1 wherein the liner acts as a getter for contaminants located at the bottom of the opening.

6. The method as recited in claim 5 wherein the liner comprises a material selected from the group consisting of:

Ti, Ta, Ru, Ir.

7. The method as recited in claim 1 wherein the method further includes forming a barrier over the liner and forming a contact plug over the barrier and within the opening.

8. The method as recited in claim 7 wherein the barrier has a thickness ranging from about 1 nm and about 4 nm, and comprises a material selected from the group consisting of TiN, TaN, TiCN, TaCN, MoN, WN, TiSiN, TaSiN, WSiN, MoSiN, MoCN and WCN.

9. The method as recited in claim 7 wherein the barrier comprises a material selected from the group consisting of Ta, Ru and Ir.

10. The method as recited in claim 7 wherein the barrier comprises a material selected from the group consist of Rh, Pd, Os, and Pt.

11. The method as recited in claim 1 wherein a lower wafer bias power is used to form an isotropic etch to remove a portion of the liner at the reentrant profile.

12. The method as recited in claim 11 wherein the wafer bias power ranges from about 100 watts to about 500 watts.

13. The method as recited in claim 1 wherein the etching includes etching with a plasma having a wafer bias power ranging from about 100 watts to about 500 watts, an RF coil power ranging from about 200 watts to about 1500 watts, a gas flow of a plasma gas having a flow rate ranging from about 10 sccm to about 100 seem, at a pressure ranging from about 1 mTorr to about 30 mTorr, wherein the plasma gas is selected from the group consisting of Ne, Ar and Xe.

14. The method as recited in claim 1 wherein the depositing and the etching are conducted simultaneously.

15. The method as recited in claim 14 wherein a DC target power of the etching ranges from about 5 kW to about 15 kW, and a wafer AC bias power of the etching ranges from about 100 Watts and 500 Watts.

16. The method as recited in claim 15 wherein an RF coil power of the etch ranges from about 200 Watts and about 1500 Watts.

17. The method as recited in claim 1 wherein an etch is conducted prior to depositing the liner.

18. The method as recited in claim 14 wherein the method further includes depositing additional liner after the simultaneous depositing and etching.

3. (canceled)

4. The method as recited in claim 3 wherein the underlying layer is a silicide layer.

19. An interconnect for use in an integrated circuit comprising:

a dielectric layer, and a conductive layer located under the dielectric layer;

an interconnect structure located within the dielectric layer, the interconnect structure, including;

a conductive plug located within an opening located in the dielectric layer;

a liner located within the opening and between the conductive plug and the dielectric layer;

a barrier located within the open and between the conductive plug and the liner, the barrier in contact with the conductive layer.

20. The interconnect as recited in claim 19 wherein at least a portion of the barrier located at the reentrant profile is deposited at the bottom of the opening.

21. The interconnect as recited in claim 19 wherein the conductive layer is a silicide layer.

22. The interconnect as recited in claim 19 wherein the liner comprises a material selected from the group consisting of:

Ti, Ta, Ru and Ir.

23. The interconnect as recited in claim 19 wherein the barrier has a thickness ranging from about 1 nm and about 4 nm, and comprises a material selected from the group consisting of TiN, TaN, TiCN, TaCN, MoN, WN, TiSiN, TaSiN, WSiN, MoSiN, MoCN and WCN.

24. The interconnect as recited in claim 19 wherein the barrier comprises a material selected from the group consisting of Ta, Ir and Ru.

25. The interconnect as recited in claim 19 wherein the barrier comprises a material selected from the group consisting of Rh, Pd, Os, and Pt.

26. A method for manufacturing an integrated circuit, comprising:

forming transistors over a semiconductor substrate;

forming a first dielectric layer over the transistors;

forming an opening in a dielectric layer,

depositing a liner over an inner surface of the opening, the depositing forming a reentrant profile near a top portion of the opening;

etching a portion of the liner, including removing at least a portion of the linear to reduce the reentrant profile and removing at least a portion of the liner at the bottom of the opening to expose an underlying layer located under the dielectric layer;

forming additional dielectric layers over the first dielectric layer; and

forming interconnects in the first dielectric layer and the additional dielectric layers to interconnect the transistors and thereby form an operative integrated circuit.

28. The method as recited in claim 26 wherein the liner comprises a material selected from the group consisting of Ti, Ta, Ru and Ir.

29. The method as recited in claim 26 wherein the method further includes depositing additional liner after the removing at least a portion of the barrier at the bottom of the opening.

30. The method as recited in claim 26 wherein the method further includes forming a barrier over the liner and forming a contact plug over the barrier and within the opening.

31. The method as recited in claim 30 wherein the barrier has a thickness ranging from about 1 nm and about 4 nm, and comprises a material selected from the group consisting of TiN, TaN, TiCN, TaCN, MoN, WN, TiSiN, TaSiN, WSiN, MoSiN, MoCN and WCN.

32. The method as recited in claim 30 wherein the barrier comprises a material selected from the group consisting of Ta, Ir and Ru.

33. The method as recited in claim 30 wherein the barrier comprises a material selected from the group consisting of Rh, Pd, Os, and Pt.

27. (canceled)

34. A method for forming an interconnect, comprising:

forming an opening in a dielectric layer over a conductive layer comprising a compound of a metal and a semiconductor;

depositing a substantially conformal liner over an inner surface of the opening, the liner comprising a metal; and

plasma etching a portion of the liner, removing at least a portion of the liner at the bottom of the opening to expose an underlying layer located under the dielectric layer.

35. The method as recited in claim 34, wherein the liner is deposited using CVD or ALD.

36. The method as recited in claim 34, wherein the liner comprises a material selected from the group consisting of TiN, TaN, TiCN, TaCN, MoN, WN, TiSiN, TaSiN, WSiN, MoSiN, MoCN and WCN.

37. (canceled)

38. The method as recited in claim 37, wherein the method further includes forming a barrier over the liner and forming a contact plug over the barrier and within the opening.

39. The method as recited in claim 38, wherein the barrier comprises a material selected from the group consisting of TiN, TaN, TiCN, TaCN, MoN, WN, TiSiN, TaSiN, WSM, MoSiN, MoCN and WCN.

40. The method as recited in claim 38, wherein the barrier comprises a material selected from the group consisting of Ru, Ir, Rh, Pd, Os, and Pt.