Contact resistance reduction by new barrier stack process
First Claim
Patent Images
1. A method for forming an interconnect, comprising:
- forming an opening in a dielectric layer, depositing a liner over an inner surface of the opening, the depositing forming a reentrant profile near a top portion of the opening; and
etching a portion of the liner, including removing at least a portion of the liner to reduce the reentrant profile and removing at least a portion of the liner at the bottom of the opening to expose an underlying layer located under the dielectric layer.
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Abstract
The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.
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Citations
40 Claims
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1. A method for forming an interconnect, comprising:
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forming an opening in a dielectric layer, depositing a liner over an inner surface of the opening, the depositing forming a reentrant profile near a top portion of the opening; and
etching a portion of the liner, including removing at least a portion of the liner to reduce the reentrant profile and removing at least a portion of the liner at the bottom of the opening to expose an underlying layer located under the dielectric layer. - View Dependent Claims (2, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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- 3. (canceled)
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19. An interconnect for use in an integrated circuit comprising:
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a dielectric layer, and a conductive layer located under the dielectric layer;
an interconnect structure located within the dielectric layer, the interconnect structure, including;
a conductive plug located within an opening located in the dielectric layer;
a liner located within the opening and between the conductive plug and the dielectric layer;
a barrier located within the open and between the conductive plug and the liner, the barrier in contact with the conductive layer. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A method for manufacturing an integrated circuit, comprising:
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forming transistors over a semiconductor substrate;
forming a first dielectric layer over the transistors;
forming an opening in a dielectric layer, depositing a liner over an inner surface of the opening, the depositing forming a reentrant profile near a top portion of the opening;
etching a portion of the liner, including removing at least a portion of the linear to reduce the reentrant profile and removing at least a portion of the liner at the bottom of the opening to expose an underlying layer located under the dielectric layer;
forming additional dielectric layers over the first dielectric layer; and
forming interconnects in the first dielectric layer and the additional dielectric layers to interconnect the transistors and thereby form an operative integrated circuit. - View Dependent Claims (28, 29, 30, 31, 32, 33)
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27. (canceled)
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34. A method for forming an interconnect, comprising:
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forming an opening in a dielectric layer over a conductive layer comprising a compound of a metal and a semiconductor;
depositing a substantially conformal liner over an inner surface of the opening, the liner comprising a metal; and
plasma etching a portion of the liner, removing at least a portion of the liner at the bottom of the opening to expose an underlying layer located under the dielectric layer. - View Dependent Claims (35, 36)
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- 37. (canceled)
Specification