Performance state-based thread management

• US 20060123251A1
• Filed: 12/02/2004
• Published: 06/08/2006
• Est. Priority Date: 12/02/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Bodas, Devadatta V., Nakajima, Jun
• Granted Patent: US 7,526,661 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods of managing threads provide for selecting a thread for execution and identifying a target performance state of a processor core based on the thread. Identifying the target performance state may include applying a priority of the thread to a mapping policy to obtain the target performance state. In one embodiment, a transition of the selected core to the target performance state can be initiated and the thread can be scheduled for execution by the processor core.

Claims

1. A method comprising:

selecting a thread for execution; and

identifying a target performance state of a processor core based on the thread.

2. The method of claim 1, further including scheduling the thread for execution by the processor core if the processor core is in the target performance state.

3. The method of claim 2, further including initiating a transition of the processor core to the target performance state if the processor core is not in the target performance state.

4. The method of claim 3, further including:

selecting the processor core from a plurality of processor cores; and

scheduling the thread for execution by the processor core if one or more remaining cores in the plurality of cores shares a performance state-dependent resource with the processor core and each of the remaining cores sharing the resource have requested at least one of the target performance state and a state that is shallower than the target performance state.

5. The method of claim 1, wherein the identifying includes applying a priority of the thread to a mapping policy to obtain the target performance state.

6. The method of claim 5, further including modifying the mapping policy based on a number of threads in a thread run queue.

7. The method of claim 6, wherein the modifying includes increasing a performance characteristic of the mapping policy if the number of threads is above a threshold.

8. The method of claim 6, wherein the modifying includes increasing a power saving characteristic of the mapping policy if the number of threads is below a threshold.

9. The method of claim 1, wherein the identifying includes identifying an Advanced Configuration and Power Interface (ACPI) P-state.

10. The method of claim 1, wherein the selecting includes searching a thread run queue for a thread having a highest priority.

11. An apparatus comprising:

a processor core; and

scheduling logic to select a thread for execution and identify a target performance state of the processor core based on the thread.

12. The apparatus of claim 11, wherein the scheduling logic is to schedule the thread for execution by the processor core if the processor core is in the target performance state.

13. The apparatus of claim 12, further including a performance state controller, the scheduling logic to send a signal to the controller to initiate a transition of the processor core to the target performance state if the processor core is not in the target performance state.

14. The apparatus of claim 13, further including a plurality of processor cores, the scheduling logic to schedule the thread for execution by the processor core if one or more remaining cores in the plurality of cores shares a performance state-dependent resource with the processor core and each of the remaining cores sharing the resource have requested at least one of the target performance state and a state that is shallower than the target performance state.

15. The apparatus of claim 11, wherein the scheduling logic is to apply a priority of the thread to a mapping policy to obtain the target performance state.

16. The apparatus of claim 15, wherein the scheduling logic is to modify the mapping policy based on a number of threads in a thread run queue.

17. The apparatus of claim 16, wherein the scheduling logic is to increase a performance characteristic of the mapping policy if the number of threads is above a threshold.

18. The apparatus of claim 16, wherein the scheduling logic is to increase a power saving characteristic of the mapping policy if the number of threads is below a threshold.

19. The apparatus of claim 11, wherein the scheduling logic is to identify an Advanced Configuration and Power Interface (ACPI) P-state.

20. The apparatus of claim 11, further including a thread run queue, the scheduling logic to search the thread queue for a thread having a highest priority.

21. A system comprising:

a random access memory to store instructions;

a chipset coupled to the memory; and

a processor coupled to the chipset, the processor having a core and scheduling logic to select a subset of the instructions as a thread for execution and identify a target performance state of the processor core based on the thread.

22. The system of claim 21, wherein the scheduling logic is to schedule the thread for execution by the processor core if the processor core is in the target performance state.

23. The system of claim 22, further including a performance state controller, the scheduling logic to send a signal to the controller to initiate a transition of the processor core to the target performance state if the processor core is not in the target performance state.

24. The system of claim 23, further including a plurality of processor cores, the scheduling logic to schedule the thread for execution by the processor core if one or more remaining cores in the plurality of cores shares a performance state-dependent resource with the processor core and each of the remaining cores sharing the resource have requested at least one of the target performance state and a state that is shallower than the target performance state.

25. A method comprising:

searching a thread run queue for a thread having a highest priority;

applying the priority of the thread to a mapping policy to obtain a target Advanced Configuration and Power Interface (ACPI) P-state;

initiating a transition of a processor core to the P-state if the processor core is not in the P-state; and

scheduling the thread for execution by the processor core is in the P-state.

26. The method of claim 25, further including:

selecting the processor core from a plurality of processor cores; and

scheduling the thread for execution by the processor core if one or more remaining cores in the plurality of cores shares a P-state-dependent resource with the processor core and each of the remaining cores sharing the P-state-dependent resource have requested at least one of the P-state and a state that is shallower than the P-state.

27. The method of claim 26 further including modifying the mapping policy based on a number of threads in the thread run queue.

28. The method of claim 27, wherein the modifying includes increasing a performance characteristic of the mapping policy if the number of threads is above a threshold.

29. The method of claim 27, wherein the modifying includes decreasing a performance characteristic of the mapping policy if the number of threads is below a threshold.

30. A machine readable medium comprising a stored set of instructions which if executed are operable to:

select a thread for execution; and

identify a target performance state of a processor core based on the thread.

31. The medium of claim 30, wherein the instructions are further operable to schedule the thread for execution by the processor core if the processor core is in the target performance state.

32. The medium of claim 31, wherein the instructions are further operable to initiate a transition of the processor core to the target performance state if the processor core is not in the target performance state.