Computer automated method for designing an integrated circuit, a computer automated system for designing an integrated circuit, and a method of manufacturing an integrated circuit

• US 20060123380A1
• Filed: 10/31/2005
• Published: 06/08/2006
• Est. Priority Date: 11/01/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ikeuchi, Atsuhiko
• Granted Patent: US 7,451,429 B2
• Time in Patent Office: Days
• US Class Current: 716/52
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group; determining one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and modifying the corresponding pattern in the candidate hot spot.

Claims

1. A computer automated method for designing an integrated circuit comprising:

placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area;

dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group;

determining one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and

modifying the corresponding pattern in the candidate hot spot.

2. The method of claim 1, further comprising:

allocating a plurality of areas on the marks taking account of an influence of the optical proximity effect before dividing the marks; and

merging adjacent areas overlapping each other into a single polygon.

3. The method of claim 1, further comprising placing an additional mark on one of the contours of the patterns based on additional mark information before dividing the marks.

4. The method of claim 1, wherein each of the patterns is defined by a rectangular regions, and placing the marks includes:

placing the marks on respective vertices of each of the rectangular regions.

5. The method of claim 1, wherein modifying the layout includes:

separating adjacent patterns apart so as to reduce the total number of marks in the candidate hot spot.

6. The method of claim 1, further comprising:

processing optical proximity correction for the chip area; and

executing a lithography rule check of the chip area after optical proximity correction is processed.

7. The method of claim 1, wherein the patterns include logical cells, high-yield cells, wires, single vias, and multicut vias implemented in a graphic image space of the chip area.

8. A computer automated system for designing an integrated circuit comprising:

a mark module configured to place a plurality of marks on each of contours of a plurality of patterns allocated in a chip area;

a grouping module configured to divide the marks into a plurality of groups so that adjacent marks are merged in a same group;

a candidate hot spot judgment module configured to judge one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and

a modification module configured to modify corresponding pattern in the candidate hot spot.

9. The system of claim 8, wherein the grouping module allocates a plurality of areas on the marks taking account of an influence of the optical proximity effect and merges adjacent areas overlapping each other into a single polygon.

10. The system of claim 8, wherein the mark module places an additional mark on one of the contours of the patterns based on additional mark information.

11. The system of claim 8, wherein each of the patterns is defined by a rectangular regions and the mark module places the marks on respective vertices of each of the rectangular regions.

12. A method of manufacturing an integrated circuit comprising:

designing layout information including patterns of cells, wires, and vias to be placed on a semiconductor substrate implemented in a graphic image space;

verifying the layout information by placing a plurality of marks on contours of the patterns, dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group, determining one of the groups as a candidate hot spot according to a total number of marks included in each of the groups, and modifying the layout based on a judged result in the graphic image space;

modifying the layout information by executing a lithography rule check;

producing a plurality of masks based on modified layout information;

forming an insulating film on the semiconductor substrate;

selectively etching a part of the insulating film by using one of the masks; and

forming corresponding actual vias and corresponding actual wires connected to the actual vias in the insulating film.

13. The method of claim 12, wherein designing layout information including patterns including logical cells, high-yield cells, wires, single vias, and multicut vias implemented in a graphic image space of the chip area.

14. The method of claim 12, wherein designing the layout information includes replacing the vias with multiple via cells based on information of a multiple via cell library,

wherein verifying the layout information includes placing the marks on contours of the multiple via cells.

15. The method of claim 12, wherein designing layout information includes expanding a routing space of the wires based on routing space information,

wherein verifying the layout information includes placing the marks on contours of wires after the routing space is expanded.

16. The method of claim 12, wherein designing layout information includes folding the wires and expanding a routing space of the wires,

wherein, verifying the layout information includes placing the marks on contours of the wires after the routing space is expanded.

17. The method of claim 12, wherein verifying the layout information further comprises:

allocating a plurality of areas on the marks taking account of an influence of the optical proximity effect before dividing the marks; and

merging adjacent areas overlapping each other into a single polygon.

18. The method of claim 12, wherein verifying the layout information further comprises placing an additional mark on one of the contours based on additional mark information before dividing the marks.

19. The method of claim 12, wherein each of the patterns are defined by a rectangular regions, and placing the mark includes:

placing the marks on respective vertices of each of the rectangular regions.

20. The method of claim 12, wherein modifying the layout includes:

separating the adjacent patterns apart so that a total number of marks in the candidate hot spot is reduced.