Inter-process interference elimination

• US 20060123430A1
• Filed: 04/29/2005
• Published: 06/08/2006
• Est. Priority Date: 12/06/2004
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Jones, Michael B., Abadi, Martin, Hunt, Galen C., Wobber, Edward P., Larus, James R., DeTreville, John D., Chilimbi, Trishul A.
• Granted Patent: US 7,694,300 B2
• Time in Patent Office: Days
• US Class Current: 719/319
• CPC Class Codes: G06F 21/562 Static detection
• CPC Class Codes: G06F 21/566 Dynamic detection, i.e. detection performed at run-time, e.g. emulation, suspicious activities
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities

Abstract

Described herein is an implementation of a technology for the construction, identification, and/or optimization of operating-system processes. At least one implementation, described herein, constructs an operating-system process having the contents as defined by a process manifest. Once constructed, the operating-system process is unalterable.

Claims

1. A computer configured with an operating system, the computer comprising:

a processor configured to execute processor-executable instruction streams of one or more operating-system processes;

a memory configured to hold one or more operating-system processes as the processor-executable instruction streams of the one or more processes are executed by a processor;

an inter-process interference eliminator configured to adjust the processor-executable instruction stream of a subject operating-system process, which is one of the one or more operating-system processes, so that the subject process, when executing, does not interfere with another executing process.

2. A computer as recited in claim 1, wherein the inter-process interference eliminator is further configured to perform the adjustment a priori execution of the processor-executable instruction stream of the subject process.

3. A computer as recited in claim 1, wherein the inter-process interference eliminator is further configured to perform the adjustment during execution of the processor-executable instruction stream of the subject process.

4. A computer as recited in claim 1, wherein the inter-process interference eliminator is further configured to analyze the processor-executable instruction stream of the subject process to determine if the subject process, when executed, has a potential to interfere with another executing process in the memory.

5. A computer as recited in claim 4, wherein the inter-process interference eliminator is further configured to perform the analysis a priori execution of the processor-executable instruction stream of the subject process.

6. A computer as recited in claim 4, wherein the inter-process interference eliminator is further configured to perform the analysis during execution of the processor-executable instruction stream of the subject process.

7. A computer as recited in claim 4, wherein the inter-process interference eliminator is further configured to, in response to a determination that the subject process, when executed, has the potential to interfere with another executing process in the memory, adjust the processor-executable instruction stream of the subject process to eliminate that potential interference.

8. A computer as recited in claim 4, wherein the processor is configured to concurrently address memory holding two or more operating-system processes as the processor-executable instruction streams of the two or more processes are executed by a processor.

9. One or more processor-readable media having processor-executable instructions that, when executed by at least one processor, perform acts comprising:

obtaining one or more operating-system processes, each process comprising a processor-executable instruction stream;

determining whether a subject operating-system process, when executing, has a potential to interfere with another operating-system process while both processes are executing, the subject operating-system process being one of the one or more operating-system processes.

10. One or more processor-readable media as recited in claim 9, the determining act being performed a priori execution of the processor-executable instruction stream of the subject operating-system process.

11. One or more processor-readable media as recited in claim 9, the determining act being performed during execution of the processor-executable instruction stream of the subject operating-system process.

12. One or more processor-readable media as recited in claim 9 further comprising, in response to a determination that the subject operating-system process, when executed, has the potential to interfere with another executing process, adjusting the processor-executable instruction stream of the subject operating-system process to eliminate that potential interference.

13. One or more processor-readable media as recited in claim 12, the adjusting act being performed a priori execution of the processor-executable instruction stream of the subject operating-system process.

14. One or more processor-readable media as recited in claim 12, the adjusting act being performed during execution of the processor-executable instruction stream of the subject operating-system process.

15. One or more processor-readable media as recited in claim 9, further comprising executing two or more operating-system processes within a common processor-addressable space in a memory.

16. One or more processor-readable media having processor-executable instructions that, when executed by at least one processor, perform acts comprising:

obtaining one or more operating-system processes, each process comprising a processor-executable instruction stream;

determining whether a subject operating-system process, when executing, has a potential to interfere with another operating-system process while both processes are executing within a common processor-addressable space in a memory, the subject operating-system process being one of the one or more operating-system processes.

17. One or more processor-readable media as recited in claim 16, the determining act being performed a priori execution of the processor-executable instruction stream of the subject operating-system process.

18. One or more processor-readable media as recited in claim 16, the determining act being performed during execution of the processor-executable instruction stream of the subject operating-system process.

19. One or more processor-readable media as recited in claim 16 further comprising, in response to a determination that the subject operating-system process, when executed, has the potential to interfere with another executing process, adjusting the process-executable instruction stream of the subject operating-system process to eliminate the potential interference.

20. One or more processor-readable media as recited in claim 19, the adjusting act being performed a priori or during execution of the processor-executable instruction stream of the subject operating-system process.