Method for calibrating semiconductor test instruments

• US 20060123882A1
• Filed: 02/11/2006
• Published: 06/15/2006
• Est. Priority Date: 06/07/2001
• Status: Active Grant

• Current Assignee: Toru Ibane
• Original Assignee: Toru Ibane
• Inventors: Ibane, Toru
• Granted Patent: US 7,107,817 B2
• Time in Patent Office: Days
• US Class Current: 73/1.420
• CPC Class Codes: G01R 31/3191 Calibration
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24
• CPC Class Codes: G01R 35/005 Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references G01R33/0035, G01R35/002 take precedence

Abstract

A method for calibrating a semiconductor test instrument leading cost reduction, simplified work, and short working time. Drivers are related to comparators in one-to-one correspondence. A clock signal and a strobe signal have a one-to-one correspondence. The phase of either a clock signal or a strobe signal is adjusted with reference to the phase of the other signal. The relative phase difference between clock signals or between strobe signals are determined. The phases of the clock and strobe signals are adjusted with reference to the relative phase difference.

Claims

1. A method for calibrating a semiconductor test instrument for performing timing calibration of a semiconductor test instrument having drivers for generating signals synchronizing with clock signals and comparators for performing comparisons synchronizing with strobe signals, comprising:

a first step of adjusting phases of one of said clock signals and said strobe signals, both of which are set in one-to-one correspondence, on the basis of the other while each of said drivers corresponds to each of said comparators;

a second step of obtaining relative phase differences between said clock signals corresponding to said drivers respectively or relative phase differences between said strobe signals corresponding to said comparators respectively; and

a third step of adjusting phases of said clock signals and phases of said strobe signals in accordance with said relative phase differences.

2. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that the phase adjustment to be executed in said first step is performed by varying phases of said clock signals so that timings for performing comparisons by said comparators in accordance with said strobe signals coincide with timings at which signals output from said drivers and input to said comparators are changed.

3. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that the phase adjustment to be executed in said first step is performed by varying phases of said strobe signals so that timings for performing comparisons by said comparators in accordance with said strobe signals coincide with timings at which signals output from said drivers and input to said comparators are changed.

4. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that the phase difference obtainment to be executed in said second step is performed by measuring phase differences of one of said clock signals and said strobe signals set in one-to-one correspondence on the basis of phase differences of the other while changing combinations of drivers with comparators in the first step.

5. The method for calibration a semiconductor test instrument according to claim 1, characterized in that a delay element for varying the phase of a signal is inserted into each of supply routes of said clock signals to said drivers and each of supply routes of said strobe signals to said comparators.

6. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that said first step is executed by using a first calibration board on which the output end of corresponding one of said drivers and the input end of corresponding one of said comparators are connected to each of a plurality of short connection points through wirings having equal time lengths.

7. The method for calibrating a semiconductor test instrument according to claim 6, characterized in that said second step is executed by using a second calibration board different from said first calibration board in combination of wirings, in which the output end of corresponding one of said drivers and the input end of corresponding one of said comparators are connected to each of a plurality of short connection points through wirings having equal time lengths.

8. The method for calibrating a semiconductor test instrument according to claim 7, characterized in that a fourth step of exchanging said first calibration board with said second calibration board is included between said first step and said second step.

9. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that

said first step is executed by using a third calibration board in which the output end of corresponding one of said drivers and the input end of corresponding one of said comparators are connected to each of a plurality of short connection points through wirings having equal time lengths, and

said second step is executed by changing over wiring states of said third calibration board so that the output end of corresponding one of said drivers and the input end of corresponding one of said comparators are connected to each of a plurality of short connection points through wirings having equal time lengths.

10. The method for calibrating a semiconductor test instrument according to claim 9, characterized in that said third calibration board includes a plurality of changeover switches for changing over wiring states and operations in said first and second steps are executed by changing over connection states of these changeover switches.

11. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that said first step is executed by using a first calibration device in which the output end of corresponding one of said drivers and the input end of corresponding one of said comparators are connected to each of a plurality of short connection points through wirings having equal time lengths.

12. The method for calibrating a semiconductor test instrument according to claim 11, characterized in that said second step is executed by using a second calibration device different from said first calibration device in combination of wirings, in which the output end of corresponding one of said drivers and the input end of corresponding one of said comparators are connected to each of a plurality of short connection points through wirings having equal time lengths.

13. The method for calibrating a semiconductor test instrument according to claim 12, characterized in that a fourth step of exchanging said first calibration device with said second calibration device by using a handler is included between said first step and said second step.

14. The method for calibrating a semiconductor test instrument according to claim 1, characterized in that said first step is executed by using a first region in a first calibration wafer in which the output end of corresponding one of said drivers and the input end of corresponding one of said comparators are connected to each of a plurality of short connection points through wirings having equal time lengths, and

said second step is executed by using a second region in a second calibration wafer different from said first calibration wafer in combination of wirings, in which the output end of corresponding one of said drivers and the input end of corresponding one of said comparators are connected to each of a plurality of short connection points through wirings having equal lengths.

15. The method for calibrating a semiconductor test instrument according to claim 14, characterized in that said first calibration wafer and said second calibration wafer are the same wafer and said first and second regions are formed in said same wafer.

16-84. -84. (canceled)