Vertical double-diffused metal oxide semiconductor (VDMOS) device incorporating reverse diode

• US 20060124994A1
• Filed: 11/02/2005
• Published: 06/15/2006
• Est. Priority Date: 12/15/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Han-Gu, Jeon, Chan-Hee, Jang, Sung-Pil
• Granted Patent: US 7,417,282 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

Abstract

The present invention disclosed herein is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device incorporating a reverse diode. This device includes a plurality of source regions isolated from a drain region. A source region in close proximity to the drain region is a first diffusion structure in which a heavily doped diffusion layer of a second conductivity type is formed in a body region of a second conductivity type. Another source region is a second diffusion structure in which a heavily doped diffusion layer of a first conductivity type and a heavily doped diffusion layer of the second conductivity type are formed in the body region of the second conductivity type. An impurity diffusion structure of the source region in close proximity to the drain region is changed to be operated as a diode, thereby forming a strong current path to ESD (Electro-Static Discharge) or EOS (Electrical Over Stress). As a result, it is possible to prevent the device from being broken down.

Claims

1. A Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device comprising:

a drain region of a first conductivity type formed on an epitaxial layer of the first conductivity type, a plurality of double diffusion source regions isolated from the drain region formed on the epitaxial layer, and a gate electrode overlapped on an upper portion of a part of the source region; and

wherein one source region in close proximity to the drain region is a first diffusion structure in which a heavily doped diffusion layer of a second conductivity type is formed in a body region of the second conductivity type,

wherein other source regions are a second diffusion structure in which a heavily doped diffusion layer of the first conductivity type and a heavily doped diffusion layer of the second conductivity type are formed in a body region of the second conductivity type.

2. The VDMOS device of claim 1, wherein the source region of the first diffusion structure and the source region of second diffusion structure are connected with interconnections.

3. The VDMOS device of claim 1, wherein when an Elecro-Static Discharge (ESD) oran Electrical Over Stress (EOS) is applied to the drain region, the drain region and the source region of the first diffusion structure operate as a diode, and the drain region and the source region of the second diffusion structure operate as a bipolar transistor.

4. The VDMOS device of claim 3, wherein a breakdown voltage of the diode is higher than a turn-on voltage of the bipolar transistor.

5. The VDMOS device of claim 1, wherein when a control signal is applied to the gate electrode, a channel of a MOS transistor is formed in the body region of the second conductivity type of the second diffusion structure.

6. The VDMOS device of claim 5, wherein when the ESD or the EOS is applied to the drain region, the drain region and the source region of the first diffusion structure operate as a diode, and the drain region and the source region of the second diffusion structure operate as a bipolar transistor, and

wherein the turn-on voltage of the bipolar transistor is higher than a threshold voltage of the MOS transistor,

wherein a reverse breakdown voltage of the diode is higher than the turn-on voltage of the bipolar transistor.

7. A Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device comprising:

an epitaxial layer of a first conductivity type formed on a substrate;

a buried diffusion layer of the first conductivity type formed at a boundary portion of the epitaxial layer and the substrate;

a drain region of the first conductivity type formed in an upper part of the epitaxial layer; and

a plurality of source regions isolated from the drain region to be formed in the upper part of the epitaxial layer,

wherein the source regions comprises;

a first source region comprising a first body region of a second conductivity type and a first heavily doped diffusion layer of the second conductivity type formed in the first body region; and

a second source region comprising a second body region, a first heavily doped diffusion layer of the first conductivity type formed in the second body region, and a second heavily doped diffusion layer of the second conductivity type,

wherein the source region in close proximity to the drain region is the first source region.

8. The VDMOS device of claim 7, wherein the first source region and the second source region are connected to each other with interconnections.

9. The VDMOS device of claim 7, wherein when an Electro-Static Discharge (ESD) or an Electrical Over Stress (EOS) is applied to the drain region, the drain region, the epitaxial layer and the first source region operate as a diode.

10. The VDMOS device of claim 7, wherein when an ESD or an EOS is applied to the drain region, the drain region, the epitaxial layer and the second source region operate as a diode.

11. The VDMOS device of claim 10, wherein the bipolar transistor comprises the heavily doped diffusion layer of the first conductivity type as an emitter region, the second body region as a base region, and the epitaxial layer as a collector region.

12. The VDMOS device of claim 7, wherein when an ESD or the EOS is applied, the epitaxial layer and the first source region operate as a diode, and the epitaxial layer and the source region operate as a bipolar transistor,

wherein a turn-on voltage of the bipolar transistor is lower than a reverse breakdown voltage of the diode.

13. The VDMOS device of claim 7, further comprising:

a gate insulating layer formed on the epitaxial layer; and

a gate electrode formed on the gate insulating layer overlapped with a first body region and a second body region,

wherein the first body region is located between the first heavily doped diffusion layer of the second conductivity type and the epitaxial layer,

wherein the second body region is located between the heavily doped diffusion layer of the first conductivity type and the epitaxial layer.

14. The VDMOS device of claim 13, wherein when a control signal is applied to the gate electrode, a channel of a Metal Oxide Semiconductor (MOS) transistor is formed in the second body region between the heavily doped diffusion layer of the first conductivity type and the epitaxial layer.

15. The VDMOS device of claim 14, wherein when the Electro-Static Discharge (ESD) or the Electrical Over Stress (EOS) is applied, the epitaxial layer and the first source region operate as a diode, and the epitaxial layer and the source region operate as a bipolar transistor,

wherein the turn-on voltage of the bipolar transistor is lower than the reverse breakdown voltage of the diode.

16. The VDMOS device of claim 15, wherein the bipolar transistor comprises the epitaxial layer as a collector region, the second body region as a base region, and the heavily doped diffusion layer of the first conductivity type as an emitter region.

17. The VDMOS device of claim 15, wherein a threshold voltage of the MOS transistor is lower than the turn-on voltage of the bipolar transistor,

wherein the turn-on voltage of the bipolar transistor is lower than the reverse breakdown voltage of the diode.