Vertical trench gate transistor semiconductor device and method for fabricating the same

• US 20060124996A1
• Filed: 12/09/2005
• Published: 06/15/2006
• Est. Priority Date: 12/14/2004
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Mizokuchi, Shuji, Tsunoda, Kazuaki
• Granted Patent: US 7,663,182 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A first region functioning as a transistor includes a drain region, a body region formed over the drain region, a source region formed over the body region and a trench formed through the body region and having a gate electrode buried therein. A source region is formed over the body region extending in a second region. The source region forming an upper edge of the trench is rounded.

Claims

1. A vertical trench gate transistor semiconductor device comprising:

a drain region;

a first body region formed over the drain region;

a second body region formed over a part of the first body region;

a first source region formed over another part of the first body region;

a second source region formed over the second body region and electrically connected to the first source region;

a trench formed through the first source region, the second source region, the first body region, and the second body region; and

a gate disposed in the trench;

wherein the second source region functions as an electrical contact for the first source region while the second body region functions as an electrical contact for the first body region, and

an upper edge of a wall face of the trench is rounded.

2. The vertical trench gate transistor semiconductor device of claim 1,

wherein the first source region and the second source region are exposed at the upper edge of the wall face of the trench, and the first source region and the second source region which are exposed at the upper edge of the wall face of the trench are rounded.

3. The vertical trench gate transistor semiconductor device of claim 1,

wherein parts of the wall face of the trench from the upper edge to upper faces of the first source region and the second source region are rounded entirely.

4. The vertical trench gate transistor semiconductor device of claim 1,

wherein a thickness of the second source region is smaller than a thickness of the first source region.

5. The vertical trench gate transistor semiconductor device of claim 1,

wherein the second source region covers an entirety of the second body region.

6. The vertical trench gate transistor semiconductor device of claim 1,

wherein an impurity concentration of an upper part of the second body region is higher than an impurity concentration of a lower part of the second body region.

7. The vertical trench gate transistor semiconductor device of claim 1,

wherein a gate region is formed so as to form a recessed part in an upper part of the trench, and

the second body region is exposed at a wall face of the recessed part.

8. The vertical trench gate transistor semiconductor device of claim 1,

wherein a gate region is formed so as to form a recessed part in an upper part of the trench, and

the first source region and the second source region are exposed at the wall face of the recessed part and are in contact through the respective exposed parts and upper faces of the respective source regions.

9. The vertical trench gate transistor semiconductor device of claim 7,

wherein the second body region includes, in an upper portion thereof, a heavily doped region of which impurity concentration is relatively high, and

the heavily doped region is exposed at the wall face of the recessed part and is in electrical contact through the exposed part.

10. The vertical trench gate transistor semiconductor device of claim 7,

wherein the second source region and the second body region are exposed at the wall face of the recessed part and are in electrical contact through the respective exposed parts.

11. The vertical trench gate transistor semiconductor device of claim 7, further comprising:

an additional electrode overlaid from the second source region to the gate region with an insulating film interposed,

wherein the additional electrode is in contact with the second source region and the second body region at the wall face of the recessed part.

34. The vertical trench gate transistor semiconductor device of claim 1,

wherein the trench has a width of 0.3 μ

m or less, and

the trench has an aspect ratio of 3 or more.

35. The vertical trench gate transistor semiconductor device of claim 34,

wherein a number of the trenches is 400 or more.

12. A vertical trench gate transistor semiconductor device comprising:

a drain region;

a first body region formed over the drain region;

a second body region formed over a part of the first body region;

a first source region formed over another part of the first body region;

a second source region formed over the second body region and electrically connected to the first source region;

a trench formed through the first source region and the first body region; and

a gate disposed in the trench;

wherein the second source region functions as an electrical contact for the first source region while the second body region functions as an electrical contact for the first body region,

an upper edge of a wall face of the trench is rounded,

a gate region is formed so as to form a recessed part in an upper part of the trench, and

the second body region is exposed at a wall face of the recessed part and is in electrical contact through the exposed part.

13. The vertical trench gate transistor semiconductor device of claim 12,

wherein the first source region and the second source region are exposed at the upper edge of the wall face of the trench, and the first source region and the second source region which are exposed at the upper edge of the wall face of the trench are rounded.

14. The vertical trench gate transistor semiconductor device of claim 12,

wherein parts of the wall face of the trench from the upper edge to upper faces of the first source region and the second source region are rounded entirely.

15. The vertical trench gate transistor semiconductor device of claim 14, further comprising:

an additional electrode overlaid from the first source region and the second source region to the gate region with an insulating film interposed,

wherein the additional electrode is in contact with the second source region and the second body region at the wall face of the recessed part.

16. The vertical trench gate transistor semiconductor device of claim 15,

wherein the additional electrode is electrically connected to the first source region and the second source region.

17. The vertical trench gate transistor semiconductor device of claim 12,

wherein the second source region is thinner than the first source region.

18. The vertical trench gate transistor semiconductor device of claim 12,

wherein the second body region includes a lower portion and an upper portion whose impurity concentration is higher than an impurity concentration of the lower portion, and

the upper portion is exposed at the wall face of the recessed part and is in electrical contact through the exposed part.

19. The vertical trench gate transistor semiconductor device of claim 18,

wherein an additional electrode is formed over the gate in the recessed part with an insulating layer interposed, and

the additional electrode is in contact with the upper portion at the wall face of the recessed part.

36. The vertical trench gate transistor semiconductor device of claim 12,

wherein the trench has a width of 0.3 μ

m or less, and

the trench has an aspect ratio of 3 or more.

37. The vertical trench gate transistor semiconductor device of claim 36,

wherein a number of the trenches is 400 or more.

20. A method for fabricating a vertical trench gate transistor semiconductor device having a first portion functioning as a transistor and a second portion functioning as an electrical contact with a body region of the transistor and arranged adjacent to the first portion, comprising:

a first step of forming a first drain region in the first portion and a second drain region in the second portion, and forming a first body region over the first drain region and a second body region over the second drain region;

a second step of forming a trench in the first body region and the second body region;

a third step of forming a first source region over the first body region;

a fourth step of forming a second source region over the second body region;

a fifth step of forming a gate within the trench so as to form a recessed part in an upper part of the trench after the second step;

a sixth step of forming an insulating film for burying the recessed part after the fifth step; and

a seventh step of removing an upper part of the insulating film and rounding an upper edge of a wall face of the recessed part,

wherein the first source region and the second source region are formed so as to be electrically connected with each other.

21. The method of claim 20,

wherein the upper part of the insulating film is removed and the upper edge of the wall face of the recessed par is rounded by dry etching in the seventh step.

22. The method of claim 21,

wherein in the seventh step, the dry etching is performed under a condition that a selection ratio of the insulating film to a material exposed at the wall face of the recessed part is in a range between 2 and 5, both inclusive.

23. The method of claim 20,

wherein the fourth step includes the step of simultaneously introducing an impurity into respective parts to be the first source region and the second source region in the first portion.

24. The method of claim 20,

wherein the second source region is formed so as to cover an entirety of the second body region.

25. The method of claim 20, further comprising:

an eighth step of forming a heavily-doped region over the second body region,

wherein in the eighth step, an impurity concentration of an upper part of the second body region is set higher than an impurity concentration of a lower part of the second body region.

26. The method of claim 20, further comprising:

a step of forming, on the insulating film, an additional electrode electrically connected to the second body region after the seventh step.

27. The method of claim 20, further comprising:

a step of forming, on the insulating film, an additional electrode electrically connected to the second source region after the seventh step.

28. The method of claim 20,

wherein in the fifth step, the second body region and the second source region are exposed at the wall face of the recessed part, and

the method further comprising the step of:

forming, on the insulating film, an additional electrode electrically connected to the second body region and the second source region after the seventh step.

29. A method for fabricating a vertical trench gate transistor semiconductor device having a first portion functioning as a transistor and a second portion functioning as an electrical contact with a body region of the transistor and arranged adjacent to the first portion, comprising:

a first step of forming a first drain region in the first portion and a second drain region in the second portion, and forming a first body region over the first drain region and a second body region over the second drain region;

a second step of forming a trench in the first body region and the second body region;

a third step of forming a gate in the trench so as to form a recessed part in an upper part of the trench and so as to expose the second body region at a wall face of the recessed part;

a fourth step of forming, in the recessed part, an additional electrode electrically connected to the second body region;

a fifth step of forming a gate in the trench so as to form a recessed part in an upper part of the trench after the second step;

a sixth step of forming an insulating film for burying the recessed part after the fifth step; and

a seventh step of removing an upper part of the insulating film and rounding an upper edge of a wall face of the recessed part after the sixth step.

30. The method of claim 29,

wherein the upper part of the insulating film is removed and the upper edge of the wall face of the recessed part is rounded by dry etching in the seventh step.

31. The method of claim 30,

wherein in the seventh step, the dry etching is performed under a condition that a selection ratio of the insulating film to a material exposed at the wall face of the recessed part is in a range between 2 and 5, both inclusive.

32. The method of claim 29, further comprising:

an eighth step of forming a heavily-doped region over the second body region,

wherein in the eighth step, an impurity concentration of an upper part of the second body region is set higher than an impurity concentration of a lower part of the second body region.

33. The method of claim 32,

wherein the upper part is exposed at the wall of the recessed part.

38. A vertical trench gate transistor semiconductor device, comprising:

a first conductivity type first semiconductor layer serving as a drain region;

a second conductivity type second semiconductor layer formed over the first semiconductor layer and serving as a body region;

a first conductivity type third semiconductor layer formed over the second semiconductor layer and serving as a source region;

a trench formed through the second semiconductor layer and the third semiconductor layer;

a gate formed in the trench; and

an electrode formed over the third semiconductor layer,

wherein a second conductivity type fourth semiconductor layer which does not reach a surface of the third semiconductor layer and is exposed at a wall face of the trench is formed in a part of the third semiconductor layer formed along a direction along which the gate extends,

the fourth semiconductor layer is electrically isolated from the gate and is electrically connected to the electrode at an upper part of the trench, and

an upper edge of the wall face of the trench is rounded.

39. The vertical trench gate transistor semiconductor device of claim 38,

wherein the third semiconductor layer is exposed at the upper edge of the wall face of the trench, and the third semiconductor layer exposed at the upper edge of the wall face of the trench is rounded.

40. The vertical trench gate transistor semiconductor device of claim 38,

wherein the a part of the wall of the trench from the upper edge to an upper face of the third semiconductor layer is rounded entirely.

41. The vertical trench gate transistor semiconductor device of claim 38,

wherein the fourth semiconductor layer is formed periodically in the third semiconductor layer along a direction along which the trench extends.

42. The vertical trench gate transistor semiconductor device of claim 38,

wherein the trench is formed in plural parts,

a width of each of the trenches is set to 0.3 μ

m or less, and

intervals between the plural trenches are set to 0.3 μ

m or less.

43. The vertical trench gate transistor semiconductor device of claim 42,

wherein each of the trenches has an aspect ratio of 3 or more.

45. The vertical trench gate transistor semiconductor device of claim 43,

wherein the third semiconductor layer is exposed at the upper edge of the wall face of the trench, and the third semiconductor layer exposed at the upper edge of the wall face of the trench is rounded.

46. The vertical trench gate transistor semiconductor device of claim 43,

wherein a part of the wall face of the trench from the upper edge to an upper face of the third semiconductor layer is rounded entirely.

44. A vertical trench gate transistor semiconductor device, comprising:

a first conductivity type first semiconductor layer serving as a drain region;

a second conductivity type second semiconductor layer formed over the first semiconductor layer and serving as a body region;

a first conductivity type third semiconductor layer formed over the second semiconductor layer and serving as a source region;

a trench formed through the second semiconductor layer and the third semiconductor layer;

a gate formed in the trench;

an insulating film formed on the gate in the trench; and

an electrode formed on the third semiconductor layer and the insulating film,

wherein a second conductivity type fourth semiconductor layer which does not reach a surface of the third semiconductor layer and is exposed at a wall face of the trench is formed in a part of the third semiconductor layer formed along a direction along which the gate extends,

the fourth semiconductor layer is electrically connected to the electrode at an upper part of the trench, and

an upper edge of the wall face of the trench is rounded.

47. The vertical trench gate transistor semiconductor device of claim 44,

wherein the fourth semiconductor layer is formed periodically in the third semiconductor layer along a direction along which the trench extends.

48. The vertical trench gate transistor semiconductor device of claim 44,

wherein the trench is formed in plural parts,

a width of each of the trenches is set to 0.3 μ

m or less, and

intervals between the plural trenches are set to 0.3 μ

m or less.

49. The vertical trench gate transistor semiconductor device of claim 48,

wherein each of the trenches has an aspect ratio of 3 or more.