Semiconductor device and method of manufacturing the same

• US 20060124997A1
• Filed: 12/13/2005
• Published: 06/15/2006
• Est. Priority Date: 12/13/2004
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Hattori, Yoshiyuki, Okada, Kyoko, Yamauchi, Shoichi
• Granted Patent: US 7,417,284 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type impurities whose concentration is lower than the first portion region constituting the combination of the cell region are formed in the semiconductor layer of the peripheral region. A field oxide layer is formed on a surface of the semiconductor upper layer.

Claims

1. A semiconductor device including a cell region in which a vertical semiconductor switching cell group is formed, and a peripheral region located on the periphery of the cell region comprising:

a semiconductor layer that is continuously formed from the cell region to the peripheral region;

an insulating layer covering the surface of the semiconductor layer in the peripheral region; and

a conductor layer covering at least the surface of the insulating layer at the cell region, wherein a super junction structure in which a combination of a first portion region extending in the layer thickness direction and including first conductivity-type impurities and a second portion region extending in the layer thickness direction and including second conductivity-type impurities is repetitively formed in a plane perpendicular to the layer thickness direction is formed in the lower region of the semiconductor layer of the cell region, a semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type impurities whose concentration is lower than the first portion region constituting the combination of the cell region are formed in the semiconductor layer of the peripheral region, and the conductor layer is connected to a main electrode at the surface side that constitutes the vertical semiconductor switching cell group.

2. The semiconductor device according to claim 1, wherein the semiconductor upper layer extends to an upper side of the super junction structure of the cell region.

3. The semiconductor device according to claim 2, wherein a source region including a high concentration of first conductivity-type impurities and a trench gate electrode which confronts through a gate insulating film the semiconductor upper layer for separating the source region and the first portion region from each other are formed in a second conductivity-type semiconductor upper layer extending to an upper side of the super junction structure.

4. A method of manufacturing a semiconductor device having a cell region having a vertical semiconductor switching cell group formed therein and a peripheral region located on a periphery of the cell region, comprising:

preparing a first conductivity-type semiconductor layer continuously extending from the cell region to the peripheral region;

forming a trench group extending from the surface of the semiconductor layer to a back surface of the semiconductor layer;

doping first conductivity-type impurities to an exposed surface of the semiconductor layer;

removing a surface neighboring region of the semiconductor layer doped with the first conductivity-type impurities; and

filling a semiconductor material including second conductivity-type impurities into the trench group.

5. The manufacturing method according to claim 4, wherein the doping of the first conductivity-type impurities includes an annealing process and further comprises exposing the exposed surface of the semiconductor layer to gas including first conductivity-type impurities.

6. The manufacturing method according to claim 4, further comprising:

removing the semiconductor material including the second conductivity-type impurities covering the surface of the semiconductor layer to expose the filled trench group after the filling of the semiconductor material; and

forming a semiconductor upper layer including second conductivity-type impurities on the surfaces of the semiconductor layer and the filled trench group including second-conductivity type impurities by crystal growth after the removing.