Transistor device having a delafossite material

• US 20060125098A1
• Filed: 02/02/2006
• Published: 06/15/2006
• Est. Priority Date: 12/17/2003
• Status: Abandoned Application

• Current Assignee: John Wager, Randy Hoffman
• Original Assignee: John Wager, Randy Hoffman
• Inventors: Hoffman, Randy, Wager, John
• Application Number:
  US11/346,029
• Publication Number:
  US 20060125098A1
• Time in Patent Office: Days
• US Class Current: 257/749
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor device includes a channel of p-type substantially transparent delafossite material. Source and drain contacts are interfaced to the channel. Gate dielectric is between a gate contact and the channel.

Claims

1. A method of using a transistor device, the transistor device comprising a channel of p-type substantially transparent delafossite material, a source contact interfaced to said channel, a drain contact interfaced to said channel, a gate contact, and a gate dielectric between said gate contact and said channel, the method comprising:

arranging the transistor device with additional transistor devices;

providing voltages to said source, drain and gate contacts to induce conduction in said channel.

2. The method of claim 1, wherein said providing voltages comprises providing a negative voltage to said gate to draw holes from one or both of said source and drain contacts.

3. The method of claim 2, further comprising providing additional voltages to operate the transistor device, said providing additional voltages comprising a providing a turn-off voltage to said gate contact.

4. The method of claim 1, wherein said arranging arranges the transistor device with additional transistor devices in a switch circuit configuration.

5. The method of claim 1, wherein said arranging arranges the transistor device with additional transistor devices in an amplifier circuit configuration.

6. The method of claim 1, wherein said arranging arranges the transistor device with additional transistor devices in a load circuit configuration.

15. The method of claim 3, further comprising:

forming an additional gate dielectric; and

forming an additional gate contact, wherein said additional dielectric and said additional gate contact is formed upon said channel and said source and drain contacts.

19. The method of claim 1, wherein forming said source and drain contacts further comprises forming said source and drain contacts upon a substrate, wherein forming said channel further comprises forming said channel upon said substrate, and wherein forming said gate dielectric further comprises forming said gate dielectric upon said source and drain contacts and said channel.

20. The method of claim 19, wherein forming said channel further comprises forming said channel of said p-type substantially transparent delafossite material using a channel material selected from the group consisting of CuScO₂, CuAlO₂, CuYO₂, CuFeO₂, CuCrO₂, CuGaO₂, CulnO₂, AgCoO₂, AgGaO₂, AglnO₂, AgScO₂, AgCrO₂, and mixtures thereof.

21. The method of claim 19, wherein forming said gate dielectric further comprises forming said gate dielectric using a dielectric material selected from the group consisting of SiO₂, Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, ZrO₂, and mixtures thereof

22. The method of claim 19, wherein forming said source, drain and gate contacts further comprises forming said source, drain and gate contacts using a doped semiconductor selected from the group consisting of GaN, BaCu₂S₂, NiO, Cu₂O, CuScO₂, CuAlO₂, CuYO₂, CuFeO₂, CuCrO₂, CuGaO₂, CulnO₂, AgCoO₂, AgGaO₂, AglnO₂, AgScO₂, AgCrO₂, and mixtures thereof

7. A method of forming a transistor device, the method comprising:

in an appropriate sequence for a desired transistor configuration, depositing thin film layers including thin film gate, source, and drain contacts, gate dielectric and a substantially transparent delafossite channel; and

at appropriate times during the appropriate sequence, patterning the thin film layers.

8. The method of claim 7, wherein depositing comprises applying solution-based deposition techniques.

9. The method of claim 8, wherein said solution-based deposition techniques comprise direct write techniques.

10. The method of claim 9, wherein said patterning comprises a lithography and etching process.

11. The method of claim 9, wherein said patterning comprises a direct-write patterning.

12. A method of forming a transistor device, the method comprising:

forming a channel of a p-type substantially transparent delafossite material;

forming a source contact interfaced to said channel;

forming a drain contact interfaced to said channel;

forming a gate contact; and

forming a gate dielectric between said gate contact and said channel.

13. The method of claim 12, wherein forming said channel further comprises forming said channel using an undoped p-type substantially transparent delafossite material.

14. The method of claim 12, wherein forming said gate contact further comprises forming said gate contact over a substrate, wherein forming said gate dielectric further comprises forming said gate dielectric upon said gate contact, and wherein forming said channel further comprises forming said channel upon said gate dielectric, wherein said additional.

16. The method of claim 12, wherein forming said channel further comprises forming said channel of said p-type substantially transparent delafossite material using a channel material selected from the group consisting of CuScO₂, CuAlO₂, CuYO₂, CuFeO₂, CuCrO₂, CuGaO₂, CulnO₂, AgCoO₂, AgGaO₂, AglnO₂, AgScO₂, AgCrO₂ and mixtures thereof.

17. The method of claim 12, wherein forming said gate dielectric further comprises forming said gate dielectric using a dielectric material selected from the group consisting of SiO₂, Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, ZrO₂, and mixtures thereof.

18. The method of claim 12, wherein forming said source, drain and gate contacts further comprises forming said source, drain and gate contacts using a doped semiconductor selected from the group consisting of GaN, BaCu₂S₂, NiO, Cu₂O, CuScO₂, CuAlO₂, CuYO₂, CuFeO₂, CuCrO₂, CuGaO₂, CulnO₂, AgCoO₂, AgGaO₂, AglnO₂, AgScO₂, AgCrO₂, and mixtures thereof.

23. The method of claim 12, wherein forming each of said source, drain and gate contacts, and said gate dielectric further comprises:

forming a transparent source contact;

forming a transparent drain contact;

forming a transparent gate contact; and

forming a transparent gate dielectric wherein a transparent device is formed.