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RFID tag design with circuitry for wafer level testing

  • US 20060125505A1
  • Filed: 12/15/2004
  • Published: 06/15/2006
  • Est. Priority Date: 12/15/2004
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • an RFID tag comprising a receive signal path from one or more primary inputs to a controller, said receive signal path to process an electrical receive signal originating from said inputs as a consequence of said inputs having received a wireless signal, a second signal path flowing into said receive signal path from a die edge of said RFID tag, said second signal path to transport an electrical test signal that emulates said receive signal while said RFID tag is being tested on wafer, said receive signal path flowing through both a first input of a logic circuit and said logic circuit'"'"'s output, said logic circuit having a second input coupled to said second signal path.

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