RFID tag with bist circuits

• US 20060125506A1
• Filed: 12/15/2004
• Published: 06/15/2006
• Est. Priority Date: 12/15/2004
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Hara, Dennis Kiyoshi, Glidden, Robert M.
• Granted Patent: US 7,380,190 B2
• Time in Patent Office: Days
• US Class Current: 324/750.300
• CPC Class Codes: G01R 31/2822 of microwave or radiofrequency circuits of attenuation, gain, e.g. using network analyzers G01R27/28
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: G01R 31/318511 Wafer Test

Abstract

Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer'"'"'s scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag'"'"'s non-volatile memory.

Claims

1. An apparatus, comprising:

an RFID tag comprising a receive signal path that flows from one or more primary inputs, said receive signal path to process an electrical receive signal originating from said inputs as a consequence of said inputs having received a wireless signal, said RFID tag also comprising a non-volatile memory, said non-volatile memory to store said RFID tag'"'"'s identification, said RFID tag including built-in-self-test (BIST) logic circuitry to test said non-volatile memory while said RFID tag is being tested on wafer.

2. The apparatus of claim 1 wherein said receive signal path flows to a controller, said controller coupled to said non-volatile memory.

3. The apparatus of claim 2 wherein said BIST logic circuitry is embedded within said controller so as to be useable through commands provided to said controller while said RFID tag is being tested on wafer.

4. The apparatus of claim 3 wherein said BIST logic circuitry comprises pseudo random data pattern generation logic circuitry to generate a pseudo random data pattern.

5. The apparatus of claim 1 wherein said BIST logic circuitry comprises pseudo random data pattern generation logic circuitry to generate a pseudo random data pattern.

6. The apparatus of claim 1 wherein said RFID tag further comprises a second signal path flowing into said receive signal path from a die edge of said RFID tag, said second signal path to transport an electrical test signal that emulates said receive signal while said RFID tag is being tested on wafer, said receive signal path flowing through both a first input of a multiplexer and said multiplexer'"'"'s output, said multiplexer having a second input coupled to said second signal path.

7. The apparatus of claim 6 wherein said second signal path traces back to an open circuit, said open circuit caused by the scribing of said wafer.

8. The apparatus of claim 7 wherein, at the region of said open circuit, said signal path flows through said RFID tag'"'"'s semiconductor substrate.

9. The apparatus of claim 6 wherein said multiplexer'"'"'s channel select input is coupled to a passive pull-up or pull-down resistor, or active equivalent, said passive pull-up or pull-down device(s) to cause said channel select input to have a first state while said RFID tag is being tested on wafer and a second state while said RFID tag is receiving said wireless signal.

10. The apparatus of claim 9 wherein said RFID tag further comprises a rectifier coupled to said input(s), a node where a supply voltage for said RFID tag is to appear residing downstream from an output of said rectifier, a diode'"'"'s cathode coupled to said node, said diode'"'"'s anode coupled to wiring that provides said RFID tag'"'"'s supply voltage while said RFID tag is being tested on wafer.

11. The apparatus of claim 1 wherein said RFID tag further comprises a rectifier coupled to said input(s), a node where a supply voltage for said RFID tag is to appear residing downstream from an output of said rectifier, a diode'"'"'s cathode coupled to said node, said diode'"'"'s anode coupled to wiring that provides said RFID tag'"'"'s supply voltage while said RFID tag is being tested on wafer.

12. A method, comprising:

applying a supply voltage to an RFID tag that has not yet been diced from its wafer, said RFID tag comprising non-volatile memory and built-in-self-test (BIST) logic circuitry, said supply voltage applied to said RFID tag at a die edge of said RFID tag for purposes of testing said non volatile memory on wafer, said testing comprising;

said BIST logic circuitry generating a write data pattern; and

,

writing said write data pattern into said non-volatile memory.

13. The method of claim 12 comprising:

reading read data from said non-volatile memory after said writing;

said BIST logic circuitry comparing said write data against read data.

14. The method of claim 13 further comprising, if said write data does not match said read data, sending an error notification from said BIST logic circuitry toward a wafer test probe.

15. The method of claim 13 further comprising, if all data written into said non-volatile memory by said BIST logic circuitry for purposes of testing said non-volatile memory has matched all of its corresponding read data read from said non volatile memory, sending an indication from said BIST logic circuitry toward a wafer test probe that indicates said non-volatile memory has passed its testing by said BIST logic circuitry.

16. The method of claim 12 wherein said BIST logic circuitry generating a write data pattern further comprises said BIST logic circuitry generating a pseudo-random pattern.

17. The method of claim 16 wherein said pseudo-random pattern is N bits long and each bit of said pseudo-random pattern corresponds to a respective one of N different addresses of said non-volatile memory.

18. The method of claim 17 wherein said N different addresses are N consecutive addresses and said non-volatile memory provides for more than N addresses, said write data pattern comprising repeating said pseudo-random pattern for a next N consecutive addresses of said non-volatile memory.