Wafer level testing for RFID tags

• US 20060125507A1
• Filed: 12/15/2004
• Published: 06/15/2006
• Est. Priority Date: 12/15/2004
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Oliver, Ronald A., Hyde, John D., Kuhn, Jay A., Glidden, Robert M., Horch, Andrew Edward
• Granted Patent: US 7,312,622 B2
• Time in Patent Office: Days
• US Class Current: 324/750.300
• CPC Class Codes: G01R 31/2822 of microwave or radiofrequency circuits of attenuation, gain, e.g. using network analyzers G01R27/28
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/318511 Wafer Test

Abstract

Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer'"'"'s scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag'"'"'s non-volatile memory.

Claims

1. A semiconductor wafer, comprising:

a reticle containing circuitry for a plurality of individual semiconductor chips separated by scribe regions, said reticle having at least one die location reserved for a wafer test probe to apply and receive test signals to test at least a group of said individual semiconductor chips, said die location wired to said individual semiconductor chips through at least one of said scribe regions so that said test signals are transported through said at least one of said scribe regions.

2. The semiconductor wafer of claim 1 wherein at least one test signal path within said scribe region comprises:

a first wiring element above said wafer'"'"'s semiconductor substrate;

a via coupled to said first element and that makes electrical contact to a conducting path that flows through said substrate beneath a scribe line;

a second via that makes electrical contact to said conducting path on an opposite side of said scribe line from said via; and

a second wiring element above said wafer'"'"'s semiconductor substrate coupled to said second via.

3. The semiconductor wafer of claim 2 wherein said reticle contains one or more die locations reserved for a wafer test probe to apply and receive respective test signals to a respective portion of said individual semiconductor chips, each one of said die locations residing in a corner or other convenient location within said reticle.

4. The semiconductor wafer of claim 3 where each of said die locations are coupled to all of said reticle'"'"'s semiconductor chips through wiring that runs through at least a portion of said reticle'"'"'s scribe regions.

5. The semiconductor wafer of claim 1 wherein said die location is said wired to said individual semiconductor chips with a multi-drop bus.

6. The semiconductor wafer of claim 1 wherein said die location is said wired to all semiconductor chips within said reticle.

7. The semiconductor wafer of claim 1 wherein each of said individual semiconductor chips comprise a receive signal path from one or more primary inputs to a controller, said receive signal path to process an electrical receive signal originating from said input(s) as a consequence of said input(s) having received a wireless signal, a second signal path flowing into said receive signal path from a die edge, said second signal path to transport an electrical test signal provided by said wafer test probe.

8. The apparatus of claim 7 wherein said receive signal path flows through both a first input of a multiplexer and said multiplexer'"'"'s output, said multiplexer having a second input coupled to said second signal path.

9. The apparatus of claim 8 wherein each of said individual semiconductor chips further comprise:

a rectifier coupled to said input, a node where a supply voltage for the semiconductor chip is to appear residing downstream from an output of said rectifier, a diode'"'"'s cathode coupled to said node, said diode'"'"'s anode coupled to supply voltage wiring that provides a supply voltage provided by said wafer test probe.

10. The apparatus of claim 9 wherein each of said semiconductor chips further comprise:

a multiplexer to multiplex between test signals generated while said semiconductor chip is being tested on wafer, said multiplexer having its power supply node coupled to said power supply wiring.

11. The semiconductor wafer of claim 1 wherein said reticle contains one or more die locations each reserved for a wafer test probe to apply and receive respective test signals to a respective portion of said individual semiconductor chips, each one of said die locations residing in a corner of said reticle, each of said redundant die locations wired to the same semiconductor chips.

12. The semiconductor wafer of claim 1 wherein each one of said semiconductor chips is an RFID tag.

13. The semiconductor wafer of claim 12 wherein at least one test signal path within said scribe and break region comprises:

a first wiring element above said wafer'"'"'s semiconductor substrate;

a via coupled to said first element and that makes electrical contact to a conducting path that flows through said substrate beneath a scribe line;

a second via that makes electrical contact to said conducting path on an opposite side of said scribe line from said via; and

a second wiring element above said wafer'"'"'s semiconductor substrate coupled to said second via.

14. The semiconductor wafer of claim 13 wherein said reticle contains four die locations reserved for a wafer test probe to apply and receive respective test signals to a respective portion of said individual RFID tags, each one of said four die locations residing in a corner of said reticle.

15. The semiconductor wafer of claim 14 where each of said four die locations are coupled to all of said reticle'"'"'s RFID tags through wiring that runs through at least a portion of said reticle'"'"'s scribe and break regions.

16. The semiconductor wafer of claim 14 where each of said four die locations are coupled to all of said reticle'"'"'s RFID tags through wiring that runs through at least a portion of said reticle'"'"'s scribe and break regions.

17. The semiconductor wafer of claim 12 wherein said die location is said wired to said individual RFID tags with a multi-drop bus.

18. The semiconductor wafer of claim 12 wherein said die location is said wired to all RFID tags within said reticle.

19. The semiconductor wafer of claim 12 wherein each of said individual RFID tags comprise a receive signal path from one or more inputs to a controller, said receive signal path to process an electrical receive signal originating from said input(s) as a consequence of said input(s) having received a wireless signal, a second signal path flowing into said receive signal path from a die edge, said second signal path to transport an electrical test signal provided by said wafer test probe.

20. The apparatus of claim 19 wherein said receive signal path flows through both a first input of a multiplexer and said multiplexer'"'"'s output, said multiplexer having a second input coupled to said second signal path.

21. The apparatus of claim 19 wherein each of said individual RFID tags further comprise:

a rectifier coupled to said input(s), a node where a supply voltage for the RFID tag is to appear residing downstream from an output of said rectifier, a diode'"'"'s cathode coupled to said node, said diode'"'"'s anode coupled to supply voltage wiring that provides a supply voltage provided by said wafer test probe.

22. The apparatus of claim 21 wherein each of said RFID tags further comprise:

a multiplexer to multiplex between test signals generated while said RFID tag is being tested on wafer, said multiplexer having its power supply node coupled to said power supply wiring.

23. The semiconductor wafer of claim 12 wherein said reticle contains one or more die locations each reserved for a wafer test probe to apply and receive respective test signals to a respective portion of said individual RFID tags, each one of said die locations residing in a corner of said reticle, each of said four redundant die locations wired to the same RFID tags through one or more redundant busses.

24. A method, comprising:

landing a wafer probe on a die site of semiconductor wafer reticle, said semiconductor wafer reticle containing RFID tags; and

,

sending a test signal from said wafer probe to each of said RFID tags, said test signal propagating through a scribe and break region of said wafer reticle.

25. The method of claim 24 wherein said RFID tags are all RFID tags within said reticle.

26. The method of claim 24 wherein said die site is in a corner of said reticle, said wafer wafer probe simultaneously on four dies sites each located in a corner of four different reticles, said die site and said reticle one of said four die sites and four reticles, respectively.

27. The method of claim 24 wherein said sending further comprises simultaneously sending said test signal from said wafer probe to said RFID tags.

28. The method of claim 24 further comprising, prior to said landing, landing said wafer probe on another die site of said reticle and moving said wafer probe from said another die site to said die site, said moving a consequence of it being determined after said landing on said another die site that testing of said RFID tags with said wafer probe at said another die site could not be properly performed.

29. The method of claim 28 wherein said RFID tags are all RFID tags within said reticle.

30. The method of claim 24 further comprising after said landing but prior to said sending:

applying a supply voltage to said RFID tags from said wafer probe.

31. The method of claim 30 wherein said applying causes each instance of a multiplexer designed within each of said RFID tags to select a particular one of its channels.

32. The method of claim 31 further comprising each of said RFID tags generating a supply voltage from its own received wireless signal after they have been diced from said wafer, said generating causing each instance of said multiplexer to select another of its channels.

33. The method of claim 30 wherein said applying causes each instance of a multiplexer designed within each of said RFID tags to be powered on, and where, each of said RFID tags generating a supply voltage from its own received wireless signal after said RFID tags have been diced from said wafer causes each instance of said multiplexer to not be powered on.

34. The method of claim 24 wherein each one of said RFID tags comprises a hardcoded identifier having a value that is unique amongst the identifiers of the other of said RFID tags, said method further comprising addressing a particular one of said RFID tags through its identifier, said test signal for commanding said particular one RFID tag to perform an operation for purposes of testing said one RFID tag on wafer.

35. The method of claim 34 wherein said commanding further comprising commanding said RFID tag to write data into its non-volatile memory.

36. The method of claim 35 wherein said write data includes a data structure that emulates said RFID tag'"'"'s identification after it has been diced from said wafer.

37. The method of claim 34 wherein said commanding further comprises commanding said RFID tag to read information from said non-volatile memory.

38. The method of claim 34 wherein said commanding further comprises commanding said RFID tag to send to said wafer probe information that emulates information said RFID tag would send to its reader after said RFID tag has been diced from said wafer.