Current cell and digital-to-analog converter using the same

• US 20060125670A1
• Filed: 10/18/2005
• Published: 06/15/2006
• Est. Priority Date: 12/09/2004
• Status: Abandoned Application

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Kim, Jong Dae, Kwon, Chong Ki, Cho, Min Hyung, Lee, Seung Chul
• Application Number:
  US11/253,181
• Publication Number:
  US 20060125670A1
• Time in Patent Office: Days
• US Class Current: 341/144
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03M 1/0863 of switching transients, e.g. glitches
• CPC Class Codes: H03M 1/742 using current sources as quantisation value generators

Abstract

Provided are a current cell and digital-to-analog converter (DAC) using the same. The current cell includes a current source; a first transistor transmitting a current produced from the current source to a first output node based on a first signal; a second transistor transmitting a current produced from the current source to a second output node based on a second signal; a first capacitor coupled between a gate of the first transistor and the second output node; and a second capacitor coupled between a gate of the second transistor and the first output node. A current mode DAC can improve in dynamic performance by using a plurality of current cells each having the above-described configuration.

Claims

1. A current cell comprising:

a current source;

a first transistor transmitting a current produced from the current source to a first output node based on a first signal;

a second transistor transmitting a current produced from the current source to a second output node based on a second signal;

a first capacitor coupled between a gate of the first transistor and the second output node; and

a second capacitor coupled between a gate of the second transistor and the first output node.

2. The current cell according to claim 1, wherein each of the first and second capacitors is equal in size to a parasitic capacitor present between the gate and a drain of each of the first and second transistors.

3. The current cell according to claim 1, wherein each of the first and second capacitors is comprised of a transistor.

4. The current cell according to claim 3, wherein the transistor is equal in size to each of the first and second transistors.

5. A digital-to-analog converter comprising:

a decoder and driver receiving N-bit digital data; and

a plurality of current cells each transmitting currents produced from a current source to a first output terminal and a second output terminal based on a signal output from the decoder and driver,

wherein each of the current cells includes;

the current source;

a first transistor transmitting a current produced from the current source to the first output terminal based on a first signal;

a second transistor transmitting a current produced from the current source to the second output terminal based on a second signal;

a first capacitor coupled between a gate of the first transistor and the second output terminal; and

a second capacitor coupled between a gate of the second transistor and the first output terminal.

6. The digital-to-analog converter according to claim 5, wherein each of the first and second capacitors is equal in size to a parasitic capacitor present between the gate and a drain of each of the first and second transistors.

7. The digital-to-analog converter according to claim 5, wherein each of the first and second capacitors is comprised of a transistor.

8. The digital-to-analog converter according to claim 7, wherein the transistor is equal in size to each of the first and second transistors.