Stacked DRAM memory chip for a dual inline memory module (DIMM)

• US 20060126369A1
• Filed: 12/10/2004
• Published: 06/15/2006
• Est. Priority Date: 12/10/2004
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Raghuram, Siva
• Granted Patent: US 7,200,021 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

The invention refers to a DRAM Memory Chip for a Dual In Line Memory Module (DIMM) having (a) a predetermined number (M) of stacked DRAM memory dies; (b) wherein each DRAM memory die is selectable by a corresponding memory rank signal (r); (c) wherein each DRAM memory die comprises an array of memory cells; (d) wherein a common internal address bus consisting of address lines is provided for addressing the memory cells and is connected to all M stacked DRAM memory dies; (e) wherein M internal data buses consisting of internal data lines are provided for writing data into the memory cells and reading data out of the memory cells of the stacked DRAM memory dies; wherein (f) an integrated redriving unit is provided which comprises: (f1) buffers for all internal address lines provided for driving external address signals applied to address pads of said DRAM memory chip and; (f2) a multiplexer/demultiplexer which switches the internal data lines of the selected DRAM memory die to data pads of said DRAM memory chip.

Claims

1. Stacked DRAM Memory Chip for a Dual In Line Memory Module having:

(a) a predetermined number of stacked DRAM memory dies;

(b) wherein each DRAM memory die is selectable by a corresponding memory rank signal;

(c) wherein each DRAM memory die comprises an array of memory cells;

(d) wherein a common internal address bus consisting of address lines is provided for addressing the memory cells and is connected to all M stacked DRAM memory dies;

(e) wherein M internal data buses consisting of internal data lines are provided for writing data into the memory cells and reading data out of the memory cells of the stacked DRAM memory dies;

 

wherein

(f) an integrated redriving unit is provided which comprises;

(f1) buffers for all internal address lines provided for driving external address signals applied to address pads of said DRAM memory chip and;

(f2) a multiplexer/demultiplexer which switches the internal data lines of the selected DRAM memory die to data pads of said DRAM memory chip.

2. Stacked DRAM Memory Chip according to claim 1 wherein the redriving unit further comprises a memory rank decoder for generating the internal memory rank signal in response to external select signals applied to control pads of the DRAM memory chip.

4. Stacked DRAM memory chip according to claim 1, wherein the multiplexer/demultiplexer is switched between a multiplexing mode and a demultiplexing mode in response to a Write Enable control signal.

5. Stacked DRAM Memory Chip according to claim 1 wherein the multiplexer/demultiplexer comprises buffers for driving the data signals transmitted via the switched data lines.

6. Stacked DRAM Memory Chip according to claim 1 wherein all DRAM memory dies are clocked by a common internal clock signal.

7. Stacked DRAM Memory Chip according to claim 6 wherein the redriving unit further comprises a buffer for driving an external clock signal applied to a clock pad of the DRAM memory chip to generate said internal clock signal.

8. Stacked DRAM Memory Chip according to claim 1 wherein the stack of DRAM memory dies and the redriving unit are integrated in the DRAM memory chip.

9. Stacked DRAM Memory Chip according to claim 1 wherein the redriving unit is powered via power supply pads of said DRAM memory chip.

3. Stacked DRAM Memory Chip according to claim 3 wherein the memory rank decoder controls the multiplexer/demultiplexer.

10. Dual In Line Memory Module comprising a plurality of stacked DRAM memory chips, wherein each stacked DRAM memory chip has:

(a) a predetermined number of stacked DRAM memory dies;

(b) wherein each DRAM memory die is selectable by a corresponding memory rank signal;

(c) wherein each DRAM memory die comprises an array of memory cells;

(d) wherein a common internal address bus consisting of address lines is provided for addressing the memory cells and is connected to all M stacked DRAM memory dies;

(e) wherein M internal data buses consisting of internal data lines are provided for writing data into the memory cells and reading data out of the memory cells of the stacked DRAM memory dies;

(f) wherein an integrated redriving unit is provided which comprises;

(f1) buffers for all internal address lines provided for driving external address signals applied to address pads of said DRAM memory chip and;

(f2) a multiplexer/demultiplexer which switches the internal data lines of the selected DRAM memory die to data pads of said DRAM memory chip.

11. Dual In Line Memory Module according to claim 10 wherein the Dual In Line Memory Module further comprises a command and address buffer chip for buffering command and address signals received from a main printed circuit board.

12. Dual In Line Memory Module according to claim 11 wherein the command and address buffer is connected via a command and address bus to all stacked DRAM memory chips mounted on a printed circuit board of said Dual In Line Memory Module.