Code tracking loop with automatic power normalization

• US 20060126574A1
• Filed: 01/24/2006
• Published: 06/15/2006
• Est. Priority Date: 10/01/2001
• Status: Active Grant

• Current Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Original Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Inventors: Bultan, Aykut, Grieco, Donald
• Granted Patent: US 7,529,292 B2
• Time in Patent Office: Days
• US Class Current: 370/335
• CPC Class Codes: H04B 1/7085 using a code tracking loop, e.g. a delay-locked loop
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04L 7/0029 interpolation of received data signal

Abstract

The present invention is for a receiver incorporated into User Equipment (UE) or base stations of a code division multiple access (CDMA) communication system. The UE and base station are in communication with one of the plurality of base stations and receives a communication signal through the receiver. The communication signal is correlated using a delay locked code tracking loop, that estimates and tracks a channel delay. The tracking loop comprises a reference code generator and an interpolator for generating timed signal versions in response to said communication. A timed signal correlator, included in the tracking loop for correlating at least two of the timed signal versions with the code reference signal. The result of the correlation is used for generating an error signal. An automatic power normalization loop (APN), that is responsive to the interpolator, generates a power error signal that normalizes the error signal through a normalization circuit.

Claims

1. A user equipment (UE) for use in a code division multiple access (CDMA) communication system including at least one base station, comprising:

a receiver for receiving a communication signal from at least one base station; and

a delay-locked code tracking loop (DCTL) for estimating and tracking a channel delay of said received communication signal, the DCTL comprising;

a reference code generator for generating a reference code signal;

an interpolator for generating a punctual output signal, an early output signal and a late output signal;

a first timed signal correlator for correlating said early output signal with said reference code signal to generate a first correlated signal;

a second timed signal correlator for correlating said late output signal with said reference code signal to generate a second correlated signal;

a third timed signal correlator for correlating said punctual output signal with said reference code signal to generate a third correlated signal;

an adder for combining the first and second correlated signals to generate a first error signal;

an automatic power normalization (APN) loop for generating a second error signal based on said third correlated signal; and

a normalization circuit for normalizing said first error signal by using said second error signal to generate a third error signal used for controlling the generation of the punctual output signal by the interpolator.

2. The UE of claim 1, wherein said APN includes:

an adder for subtracting said third correlated signal from a power reference signal, to produce a power difference signal; and

a filter, responsive to said adder, for filtering said power difference signal to generate said second error signal.

3. The UE of claim 2 further comprising:

a loop filter, coupled to said normalization circuit, for filtering said third error signal;

an accumulator, responsive to said loop filter, for accumulating said third error signal;

a gain circuit, coupled to the accumulator, for changing the sign in said third error signal to correct a timing delay/advance of the received communication signal to the reference code signal; and

a quantizer for generating a discrete value of the delay/advance for controlling the generation of the punctual output signal by the interpolator.

4. The UE of claim 3, wherein said early output signal is a half chip earlier than said punctual output signal and said late output signal is a half chip later than said punctual output signal.

5. The UE of claim 3, wherein the loop filter is a first order low-pass filter.

6. The UE of claim 3, wherein the loop filter is a classical proportional integrator (PI) filter.

7. The UE of claim 3, wherein the accumulator is equipped with overflow detection to limit the output value of the accumulator.

8. The UE of claim 3, wherein the quantizer is a 32 level quantizer for obtaining an accuracy of Tc/16, where Tc is the chip duration using the multi-path search algorithm.

9. The UE of claim 1, wherein the APN further includes a limiter for preventing noise amplification.

10. The UE of claim 9, wherein the limiter limits the multiplication factor from 0.1 to 10.

11. The UE of claim 9, wherein the limiter limits the multiplication factor to −

20 dB to 20 dB.