Flow assignment

• US 20060126628A1
• Filed: 12/13/2004
• Published: 06/15/2006
• Est. Priority Date: 12/13/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Li, Yunhong, Khobare, Abhijit S.
• Granted Patent: US 7,564,847 B2
• Time in Patent Office: Days
• US Class Current: 370/392
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

In general, in one aspect, the disclosure describes assigning a flow of network packets to a thread of a multi-threaded processor core in a set of multiple multi-threaded processor cores integrated on a single die. Based on the assigning, a packet in the flow is processed by the assigned processor core thread.

Claims

1. A method, comprising:

assigning a flow of network packets to a thread of a multi-threaded processor core in a set of multiple multi-threaded processor cores integrated on a single die;

based on the assigning, processing a packet in the flow by the assigned processor core thread.

2. The method of claim 1, wherein the packet comprises an Internet Protocol packet including a Transmission Control Protocol segment.

3. The method of claim 2, wherein the flow comprises a flow identified by, at least, the packet'"'"'s Internet Protocol source address, Internet protocol destination address, Transmission Control Protocol segment source port, and Transmission Control Protocol segment destination port.

4. The method of claim 1, further comprising determining whether each packet in the flow that has been scheduled to be processed by the core thread has been processed.

5. The method of claim 1, further comprising reading data associated with the flow into a local memory associated with processor core.

6. The method of claim 5, wherein the data comprises a Transmission Control Block (TCB) of a Transmission Control Protocol (TCP) connection.

7. The method of claim 1, further comprising:

determining at a first processor core the processor core assigned to the flow;

determining at the assigned processor core one of a set of threads assigned to the flow.

8. An article of manufacture, comprising instructions for causing a multi-core processor to:

assign a flow of network packets to a thread of a multi-threaded processor core in a set of multiple multi-threaded processor cores integrated on a single die; and

based on the assignment, process a packet in the flow by the assigned processor core thread.

9. The article of claim 8, wherein the packet comprises an Internet Protocol packet including a Transmission Control Protocol segment.

10. The article of claim 8, further comprising instructions to determine whether each packet in the flow that has been scheduled to be processed by the core thread has been processed.

11. The article of claim 8, further comprising reading data associated with the flow into a local memory associated with processor core.

12. The article of claim 11, wherein the data comprises a Transmission Control Block (TCB) of a Transmission Control Protocol (TCP) connection.

13. The article of claim 8, further comprising instructions to:

determine at a first processor core the processor core assigned to the flow;

determine at the assigned processor core one of a set of threads assigned to the flow.

14. An apparatus, comprising:

multiple multi-threaded processor cores integrated on a single die; and

instructions to cause at least some of the multiple multi-threaded processor cores to;

assign a Transmission Control Protocol/Internet Protocol (TCP/IP) flow to a one of the threads of the processor cores; and

based on the assignment, process a TCP segment in the flow by the assigned processor core thread.

15. The apparatus of claim 14,

wherein the processor comprises at least one Content Addressable Memory;

and

wherein the instructions to assign the TCP/IP flow to the one of the threads comprises instructions to write a flow identifier into the at least one Content Addressable Memory.