Method, system, and apparatus for system level initialization

• US 20060126656A1
• Filed: 12/13/2004
• Published: 06/15/2006
• Est. Priority Date: 12/13/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ayyar, Mani, Kumar, Akhilesh, Jayasimha, Doddaballapur N., Chennupaty, Srinivas, Mannava, Phanindra K., Nachimuthu, Murugasamy
• Granted Patent: US 7,738,484 B2
• Time in Patent Office: Days
• US Class Current: 370/453
• CPC Class Codes: H04L 67/125 involving control of end-device applications over a network
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC

Abstract

Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.

Claims

1. An apparatus to Power on Clear (POC) value in a point-to-point (pTp) architecture comprising:

an I/O agent to derive the POC value from a plurality of straps; and

the I/O agent to forward the POC value to a plurality of processors that adhere to the pTp architecture over a plurality of point to point links.

2. The apparatus of claim 1, wherein the POC value is either one of the following:

Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.

3. A method for establishing Power on Clear (POC) value in a point-to-point (pTp) architecture comprising:

deriving the POC value from a plurality of straps; and

forwarding the POC value to a plurality of processors.

4. The method of claim 3, wherein the POC value is either one of the following:

Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.

5. The method of claim 3, wherein the pTp architecture adheres to a layered protocol scheme.

6. A method for establishing Power on Clear (POC) value in a point-to-point (pTp) architecture comprising:

an Input Output (IO) agent to obtain the POC value from either a local non volatile memory (NVM) or from a firmware space; and

forwarding the POC value to a plurality of processors.

7. The method of claim 6, wherein the POC value is either one of the following:

Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.

8. The method of claim 6, wherein the pTp architecture adheres to a layered protocol scheme.

9. A method for establishing Power on Clear (POC) value in a point-to-point (pTp) architecture comprising:

an Input Output (IO) agent to obtain the POC value from a downstream chipset with a protocol; and

the IO agent to obtain the POC value prior to a point to point link initialization.

10. The method of claim 9, wherein the POC value is either one of the following:

Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.

11. The method of claim 9, wherein the pTp architecture adheres to a layered protocol scheme.

12. A method for link layer for component or system initialization comprising:

initializing a physical layer to permit electrical transfer of information between a first and second agent;

performing a link layer initialization for the first and second agent by exchanging a plurality of control flits for link layer control messages and initialization,; and

transmitting one or more control flits to initialize a component that adheres to a pTp architecture.

13. The method of claim 12, wherein the control flits for the link layer initialization comprise:

values for flit framing, error detection and recovery policy, interleaving policy, virtual channel, and flow control capability.

14. The method of claim 12, wherein the control flits for the initialization comprise the following:

i) SBSP indicator, Built in self test (BIST), Processor to Platform Clock Ratio, Authentication of external Firmware, Burn in Testing,

ii) Indication of cores that should remain inactive for avoiding defective cores or implementing licensing restrictions and Capacity on Demand feature

iii) Platform Topology index, that may be used by the firmware to obtain values for programming the Route tables and other interconnect fabric using data from the firmware, non-volatile memory (NVM) or other platform resource.

iv) Indication to a Memory controller to preserve the memory contents.

v) Indication to an IO agent that the processor socket incorporates bridges, hubs and devices that are logically downstream from the IO agent.

15. A method for link layer for component or system initialization comprising:

initializing a physical layer to permit electrical transfer of information between a first and second agent;

performing a link layer initialization for the first and second agent by exchanging a plurality of control flits for link layer control messages and initialization; and

transmitting one or more control flits to initialize a component that adheres to a pTp architecture from an IO agent to a CPU.

16. The method of claim 15, wherein the control flits for the link layer initialization comprise:

values for flit framing, error detection and recovery policy, interleaving policy, virtual channel, and flow control capability.

17. The method of claim 15, wherein the control flits for the initialization comprise the following:

i) SBSP indicator, Built in self test (BIST), Processor to Platform Clock Ratio, Authentication of external Firmware, Burn in Testing,

ii) Indication of cores that should remain inactive for avoiding defective cores or implementing licensing restrictions and Capacity on Demand feature

iii) Platform Topology index, that may be used by the firmware to obtain values for programming the Route tables and other interconnect fabric using data from the firmware, non-volatile memory (NVM) or other platform resource.

iv) Indication to a Memory controller to preserve the memory contents.

v) Indication to an IO agent that the processor socket incorporates bridges, hubs and devices that are logically downstream from the IO agent.

19. The method of claim 16, wherein the control flits for the link layer initialization comprise:

values for flit framing, error detection and recovery policy, interleaving policy, virtual channel, and flow control capability.

i) SBSP indicator, Built in self test (BIST), Processor to Platform Clock Ratio, Authentication of external Firmware, Burn in Testing,

ii) Indication of cores that should remain inactive for avoiding defective cores or implementing licensing restrictions and Capacity on Demand feature

iii) Platform Topology index, that may be used by the firmware to obtain values for programming the Route tables and other interconnect fabric using data from the firmware, non-volatile memory (NVM) or other platform resource.

iv) Indication to a Memory controller to preserve the memory contents.

v) Indication to an IO agent that the processor socket incorporates bridges, hubs and devices that are logically downstream from the IO agent.

18. A method for a link layer for component or system initialization comprising:

initializing a physical layer to permit electrical transfer of information between a first and second agent;

performing a link layer initialization for the first and second agent by exchanging a plurality of control flits for link layer control messages and initialization; and

transmitting one or more control flits to initialize a component that adheres to a pTp architecture from an IO agent to a CPU.

20. A system that adheres to a pTp architecture and facilitates initialization comprising:

A plurality of processor agents and memory agents coupled to a network fabric a physical layer that is initialized to permit electrical transfer of information between a first and second agent of either the plurality of processor agents or memory agents, coupled to the network fabric;

a link layer initialization that is initialized for the first and second agent by exchanging a plurality of control flits for link layer control messages and initialization; and

the physical layer to transmit one or more control flits to initialize a component that adheres to the pTp architecture.

21. The system of claim 20, wherein the pTp architecture adheres to a layered protocol scheme.

22. The system of claim 20, wherein the control flits for the link layer initialization comprise:

values for flit framing, error detection and recovery policy, interleaving policy, virtual channel, and flow control capability.

23. The system of claim 20, wherein the control flits for the initialization comprise the following:

i) SBSP indicator, Built in self test (BIST), Processor to Platform Clock Ratio, Authentication of external Firmware, Burn in Testing,

ii) Indication of cores that should remain inactive for avoiding defective cores or implementing licensing restrictions and Capacity on Demand feature

iii) Platform Topology index, that may be used by the firmware to obtain values for programming the Route tables and other interconnect fabric using data from the firmware, non-volatile memory (NVM) or other platform resource.

iv) Indication to a Memory controller to preserve the memory contents.

v) Indication to an IO agent that the processor socket incorporates bridges, hubs and devices that are logically downstream from the IO agent.

24. An apparatus to derive a plurality of unique node identifiers (NodeIDs) in a point-to-point architecture comprising:

a chipset, coupled to a uni-processor, via a network fabric that adheres to the pTp architecture; and

the uni-processor to utilize default NodeID values for chipset and the uni-processor.

25. An system to derive a plurality of unique node identifiers (NodeIDs) in a point to point architecture comprising:

a plurality of hardware straps to define the NodeIDs that are read by an component that adheres to the pTp architecture and to initialize internal registers representing the NodeIDs;

a plurality of bits to be suffixed to the values in the internal registers if the component is to support multiple agents, and to instantiate required unique NodeID values.

26. An apparatus to derive a plurality of unique node identifiers (NodeIDs) in a point-to-point architecture comprising:

a component that adheres to the pTp architecture; and

a Service processor to set the component'"'"'s plurality of registers with unique NodeID values using server management channels.

27. The apparatus of claim 26, wherein the server management channels are either JTAG or SMBUS.

28. A chipset to derive a plurality of unique node identifiers (NodeIDs) in a point-to-point architecture comprising:

the chipset to assign NodeIDs to a plurality of processor agents using a link layer parameter exchange protocol;

a plurality of point to point links complete their physical layer initialization and send a link layer control flit to relevant agents;

the plurality of processor agents to sending Null Control flits to each other and to the chipset over their respective point to point link;

the chipset to send a predetermined exchange parameter control flit that specifies the chipset'"'"'s NodeID and a link port number on the chipset through which it is connected to the processor agents; and

the processor agents use the link port number as their own NodeID.

29. A method for adding an individual resource to a point-to-point architecture system comprising:

adding the individual resource to the system without requiring a reboot; and

recognizing a plurality of characteristics of the added individual resource by use of an agent type field in a link layer parameter exchange