Compact system module with built-in thermoelectric cooling

• US 20060128059A1
• Filed: 02/01/2006
• Published: 06/15/2006
• Est. Priority Date: 08/31/1998
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard, Cloud, Eugene H.
• Application Number:
  US11/345,253
• Publication Number:
  US 20060128059A1
• Time in Patent Office: Days
• US Class Current: 438/108
• CPC Class Codes: G02B 6/4214 the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device G02B6/4246 takes precedence
• CPC Class Codes: G02B 6/4232 using the surface tension of fluid solder to align the elements, e.g. solder bump techniques flip-chip mounting techniques in assembly of semiconductor devices H01L24/81
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/854 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/345 Arrangements for heating thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/38 Cooling arrangements using the Peltier effect
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/167 : comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/645 : the elements being electrically controlled, e.g. Peltier elements
• CPC Class Codes: Y10S 257/93 : Thermoelectric, e.g. peltier effect cooling

Abstract

An improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The improved integrated circuit package does not require changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. The packaging includes a Peltier element.

Claims

1. A method for packaging an integrated circuit, comprising:

providing a silicon interposer having opposing sides;

coupling a semiconductor chip to each of the opposing sides of the silicon interposer;

coupling the semiconductor chips on each side of the silicon interposer to one another through the silicon interposer by a number of micro-machined vias, wherein the micro-machined vias provide electrical connections between the opposing sides of the silicon interposer;

coupling a metal-to-semiconductor junction to at least one of the semiconductor chips, wherein the semiconductor includes a doped complex oxide semiconductor.

2. The method of claim 1, wherein coupling a doped complex oxide semiconductor includes coupling an n-doped complex oxide semiconductor comprising Strontium (Sr) and Titanium (Ti).

3. The method of claim 1, wherein coupling a doped complex oxide semiconductor includes coupling an oxygen deficient an n-doped complex oxide semiconductor.

4. The method of claim 1, wherein the semiconductor chips include a flip chip.

5. The method of claim 4, wherein a Peltier element is coupled to a flip chip.

6. The method of claim 1, wherein the semiconductor chips includes a memory chip.

7. The method of claim 6, wherein the memory chip includes at least one of a dynamic random access memory (DRAM) chip, a flash memory chip and a static random access memory (SRAM) chip.

8. The method of claim 6, wherein the semiconductor chips include capacitors.

9. A method for packaging an integrated circuit, comprising:

providing a silicon interposer having opposing sides;

coupling a semiconductor chip to each of the opposing sides of the silicon interposer;

coupling the semiconductor chips on each side of the silicon interposer to one another through the silicon interposer by a number of micro-machined vias, wherein the micro-machined vias provide electrical connections between the opposing sides of the silicon interposer;

coupling a metal-to-semiconductor junction to at least one of the semiconductor chips, wherein the semiconductor includes an n-doped superlattice comprising alternating layers of (PbTeSe)m and (BiSb)n, where m and n are the number of PbTeSe and BiSb monolayers per superlattice period.

10. The method of claim 9, wherein the semiconductor chips include a flip chip.

11. The method of claim 10, wherein a Peltier element is coupled to a flip chip.

12. The method of claim 9, wherein the semiconductor chips includes a memory chip.

13. The method of claim 12, wherein the memory chip includes at least one of a dynamic random access memory (DRAM) chip, a flash memory chip and a static random access memory (SRAM) chip.

14. The method of claim 12, wherein the semiconductor chips include capacitors.

15. A method for packaging an integrated circuit, comprising:

providing a silicon interposer having opposing sides;

coupling a semiconductor chip to each of the opposing sides of the silicon interposer;

coupling the semiconductor chips on each side of the silicon interposer to one another through the silicon interposer by a number of micro-machined vias, wherein the micro-machined vias provide electrical connections between the opposing sides of the silicon interposer;

coupling a metal-to-semiconductor junction to at least one of the semiconductor chips, wherein the semiconductor includes either an n or p-doped semiconductor alloy formed between Antimony (Sb) and transition metal (T) from Group VIII, including Cobalt (Co), Rhodium (Rh), and Iridium (Ir), and wherein the alloy has the general formula TSb3.

16. The method of claim 15, wherein the semiconductor chips include a flip chip.

17. The method of claim 16, wherein a Peltier element is coupled to a flip chip.

18. The method of claim 15, wherein the semiconductor chips includes a memory chip.

19. The method of claim 16, wherein the memory chip includes at least one of a dynamic random access memory (DRAM) chip, a flash memory chip and a static random access memory (SRAM) chip.

20. The method of claim 16, wherein the semiconductor chips include capacitors.

21. A method for cooling an integrated circuit, comprising:

providing a silicon interposer having opposing sides;

coupling a first semiconductor chip to a first side of the silicon interposer;

coupling a second semiconductor chip to a second side of the silicon interposer, wherein a number of electrical connections through the silicon interposer couple the first semiconductor chip to the second semiconductor chip;

forming a metal-to-semiconductor junction which couples to the first semiconductor chip on the first side of the silicon interposer, wherein forming the metal-to-semiconductor junction includes forming a Copper (Cu) and n or p-doped semiconductor junction, wherein the semiconductor is selected from Bismuth Telluride (Bi2Te3), Lead Telluride (PbTe), and Silicon Germanium (SiGe); and

passing current through the metal-to-semiconductor junction in a direction such that a Peltier cooling effect occurs adjacent to the first semiconductor chip.

22. The method of claim 21, wherein the semiconductor chips include a flip chip.

23. The method of claim 22, wherein a Peltier element is coupled to a flip chip.

24. The method of claim 21, wherein the semiconductor chips includes a memory chip.

25. The method of claim 24, wherein the memory chip includes at least one of a dynamic random access memory (DRAM) chip, a flash memory chip and a static random access memory (SRAM) chip.

26. The method of claim 21, wherein the semiconductor chips include capacitors.

27. A method for cooling an integrated circuit, comprising:

providing a silicon interposer having opposing sides;

coupling a first plurality of semiconductor chips to a first side of the silicon interposer;

coupling at least one Peltier element to one of the first side of the silicon interposer and on of the first plurality of semiconductor chips; and

coupling a second plurality of semiconductor chips to a second side of the silicon interposer wherein a number of electrical connections through the silicon interposer couple the first plurality of semiconductor chips to the second plurality of semiconductor chips.

28. The method of claim 27, wherein the first plurality of semiconductor chips includes flip chips, and the at least one Peltier element is coupled to a selected one of the flip chips.

29. The method of claim 27, wherein the second plurality of semiconductor chips includes a memory chip.

30. The method of claim 29, wherein the memory chip includes at least one of a dynamic random access memory (DRAM) chip, a flash memory chip and a static random access memory (SRAM) chip.

31. The method of claim 29, wherein the second plurality includes semiconductor chip capacitors.