Independently accessed double-gate and tri-gate transistors in same process flow
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Abstract
A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device.
113 Citations
20 Claims
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1-10. -10. (canceled)
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11. An integrated circuit formed by a process that includes:
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forming at least two semiconductor bodies, wherein the semiconductor bodies have overlying insulative members;
forming a sacrificial layer over the at least two semiconductor bodies and their overlying insulative members;
planarizing the sacrificial layer;
patterning the sacrificial layer to form a gate-defining member;
forming a dielectric material adjacent the gate-defining member;
covering a remaining portion of one of the insulative members;
removing a remaining portion of another one of the insulative members;
removing the gate-defining member; and
forming an insulative layer and gate electrode layer within a trench defined by removal of the gate-defining member. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification