Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes

• US 20060128137A1
• Filed: 12/09/2004
• Published: 06/15/2006
• Est. Priority Date: 12/09/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Furukawa, Toshiharu, Mitchell, Peter H., Holmes, Steven John, Koburger, Charles William III, Hakey, Mark Charles, Horak, David Vaclav
• Granted Patent: US 7,229,909 B2
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/842 for carbon nanotubes or fullerenes

Abstract

A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, by depositing a conventional dielectric on the surface to fill the area between the carbon nanotubes, and by then removing the carbon nanotubes to produce voids in place of the carbon nanotubes. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.

Claims

1. A method of making an integrated circuit chip, comprising the steps of:

providing a chip substrate having a plurality of active devices formed therein;

forming a plurality of cylindrical form structures on a surface of said integrated circuit chip;

depositing a layer of dielectric over said surface of said integrated circuit chip to surround said cylindrical form structures;

removing said cylindrical form structures to create a dielectric layer structure having voids therein; and

forming a plurality of discrete conductors in said dielectric layer structure.

2. The method of claim 1, wherein said cylindrical form structures are carbon nanotubes.

3. The method of claim 2, wherein said step of forming a plurality of cylindrical form structures on a surface of said integrated chip comprises:

forming a plurality of catalyst particles on said surface of said integrated circuit chip; and

growing said plurality of carbon nanotubes in a substantially perpendicular orientation from said plurality of catalyst particles.

4. The method of claim 3, wherein said step of forming a plurality of catalyst particles on said surface of said integrated circuit chip comprises:

depositing a metallic base film for said catalyst particles; and

processing said integrated circuit chip having deposited therein said metallic base film in an electrolyte solution to deposit catalyst particles by pulse-current electrochemical deposition.

5. The method of claim 3, wherein said step of forming a plurality of catalyst particles on said surface of said integrated circuit chip comprises:

depositing a monolayer of polystyrene beads on said surface of said integrated circuit chip;

sputter depositing said catalyst onto said surface of said integrated circuit chip through spaces in said polystyrene beads; and

removing said monolayer of polystyrene beads.

6. The method of claim 3, wherein said step of forming a plurality of catalyst particles on said surface of said integrated circuit chip comprises:

depositing a film of a catalyst material on said surface of said integrated circuit chip; and

lithographically defining a pattern of discrete catalyst particles in said film.

7. The method of claim 1, wherein said dielectric layer structure is formed as a dielectric layer between two conductive layers of said integrated circuit chip, said plurality of discrete conductors in the dielectric layer comprising vias connecting respective pairs of conductors in said two conductive layers.

8. The method of claim 1, wherein said dielectric layer structure is formed as a dielectric isolation structure within a conductive layer of said integrated circuit chip, said plurality of discrete conductors in the dielectric layer comprising discrete horizontally oriented conductors within said conductive layer of said integrated circuit chip.

9. The method of claim 1, wherein said method comprises forming a plurality of said dielectric layer structures in said integrated circuit chip, each layer containing a respective plurality of said voids.

10. The method of claim 1, wherein said step of forming a plurality of discrete conductors in said dielectric layer structure comprises:

patterning said dielectric to create a plurality of recesses in respective locations corresponding to said plurality of discrete conductors, said step of patterning said dielectric being performed before said step of removing said cylindrical form structures; and

depositing a conductive material in said plurality of recesses to create said plurality of discrete conductors.

11. The method of claim 1, wherein said step of forming a plurality of discrete conductors in said dielectric layer structure comprises:

patterning said dielectric to create a plurality of recesses in respective locations corresponding to said plurality of discrete conductors, said step of patterning said dielectric being performed after said step of removing said cylindrical form structures; and

depositing a conductive material in said plurality of recesses to create said plurality of discrete conductors.

12. An integrated circuit chip having a plurality of substantially planar parallel layers deposited over a substrate, including:

a first plurality of substantially planar parallel conductor layers, each conductor layer comprising a plurality of discrete conductors separated by a dielectric;

a second plurality of substantially planar parallel insulative layers, each insulative layer comprising a dielectric penetrated by a plurality of conductive vias;

at least one of said layers comprising a dielectric structure containing a plurality of cylindrical voids therein, said cylindrical voids being oriented perpendicular to said at least one layer, said cylindrical voids being substantially smaller than said conductive vias.

13. The integrated circuit chip of claim 12, wherein said cylindrical voids have a diameter of less than 50 nm.

14. The integrated circuit chip of claim 13, wherein said cylindrical voids have a diameter of less than 30 nm.

15. The integrated circuit chip of claim 12, wherein said at least one layer comprising a dielectric structure is at least one layer of said first plurality of layers.

16. The integrated circuit chip of claim 12, wherein said at least one layer comprising a dielectric structure is at least one layer of said second plurality of layers.

17. A method of making an integrated circuit chip, comprising the steps of:

providing a chip substrate having a plurality of active devices formed therein;

forming a plurality of substantially planar parallel layers over said chip substrate, including (a) a first plurality of substantially planar parallel conductor layers, each conductor layer comprising a plurality of discrete conductors separated by a dielectric, and (b) a second plurality of substantially planar parallel insulative layers, each insulative layer comprising a dielectric penetrated by a plurality of conductive vias

wherein said step of forming a plurality of substantially planar parallel layers comprises forming a dielectric structure containing a plurality of cylindrical voids within at least one of said layers, said cylindrical voids being oriented perpendicular to said at least one layer, said cylindrical voids being substantially smaller than said conductive vias.

18. The method of making an integrated circuit chip of claim 17, wherein said step of forming a dielectric structure containing a plurality of cylindrical voids within at least one of said layers comprises the steps of:

forming a plurality of cylindrical forms structures on a surface of said integrated circuit chip;

depositing a dielectric material over said surface of said integrated circuit chip to surround said cylindrical form structures;

removing said cylindrical form structures to create said dielectric structure containing a plurality of cylindrical voids.

19. The method of making an integrated circuit chip of claim 18, wherein said cylindrical form structures are carbon nanotubes.

20. The method of making an integrated circuit chip of claim 17, wherein said dielectric layer structure is formed as one of said insulative layers between two conductor layers of said integrated circuit chip, said plurality of discrete conductors in the insulative layer comprising vias connecting respective pairs of conductors in said two conductor layers.

21. The method of making an integrated circuit chip of claim 17, wherein said dielectric layer structure is formed as a dielectric isolation structure within one of said conductor layers of said integrated circuit chip, said plurality of discrete conductors in the dielectric layer comprising discrete horizontally oriented conductors within said conductor layer of said integrated circuit chip.

22. A method of forming a dielectric insulative structure, comprising the steps of:

forming a plurality of cylindrical form structures on a surface, said cylindrical form structures being oriented substantially perpendicular to said surface;

depositing a layer of dielectric over said surface to surround said cylindrical form structures;

removing said cylindrical form structures to create a dielectric insulative structure having voids therein.

23. The method of claim 22, wherein said cylindrical form structures are carbon nanotubes.

24. The method of claim 23, wherein said step of forming a plurality of cylindrical form structures on a surface comprises:

forming a plurality of catalyst particles on said surface; and

growing said plurality of carbon nanotubes in a substantially perpendicular orientation from said plurality of catalyst particles.

25. The method of claim 22, wherein said dielectric insulative structure is formed as a layer of an integrated circuit chip.

26. A method of forming a dielectric layer within an integrated circuit chip, comprising the steps of:

forming a plurality of carbon nanotubes on a surface of said integrated circuit chip;

depositing a layer of dielectric over said surface of said integrated circuit chip to surround said carbon nanotubes;

removing said carbon nanotubes to create said dielectric layer structure, said dielectric layer structure having voids therein.

27. The method of claim 26, wherein said step of forming a plurality of carbon nanotubes on a surface of said integrated chip comprises:

forming a plurality of catalyst particles on said surface of said integrated circuit chip; and

growing said plurality of carbon nanotubes in a substantially perpendicular orientation from said plurality of catalyst particles.

28. The method of claim 27, wherein said step of forming a plurality of catalyst particles on said surface of said integrated circuit chip comprises:

depositing a metallic base film for said catalyst particles; and

processing said integrated circuit chip having deposited therein said metallic base film in an electrolyte solution to deposit catalyst particles by pulse-current electrochemical deposition.

29. The method of claim 27, wherein said step of forming a plurality of catalyst particles on said surface of said integrated circuit chip comprises:

depositing a monolayer of polystyrene beads on said surface of said integrated circuit chip;

sputter depositing said catalyst onto said surface of said integrated circuit chip through spaces in said polystyrene beads; and

removing said monolayer of polystyrene beads.

30. The method of claim 27, wherein said step of forming a plurality of catalyst particles on said surface of said integrated circuit chip comprises:

depositing a film of a catalyst material on said surface of said integrated circuit chip; and

lithographically defining a pattern of discrete catalyst particles in said film.