Method and apparatus for accessing memory in a computer system architecture supporting heterogeneous configurations of memory structures

• US 20060129741A1
• Filed: 12/15/2004
• Published: 06/15/2006
• Est. Priority Date: 12/15/2004
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hillier, Philip Rogers III, Kirscht, Joseph Allen, Kuesel, Jamie Randall
• Granted Patent: US 7,970,980 B2
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture

Abstract

A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main memory, and memory access control logic which controls the routing of data and access to memory. The communications medium and memory access control logic are designed to accommodate a heterogenous collection of main memory configurations, in which at least one physical parameter is variable for different configurations. The bits of the memory address are mapped to actual memory locations by assigning fixed bit positions to the most critical physical parameters across multiple different module types, and assigning remaining non-contiguous bit positions to less critical physical parameters. In the preferred embodiment, the computer system employs a distributed memory architecture.

Claims

1. A digital data processing system, comprising:

at least one processor;

a plurality of memory modules embodying a main memory;

a communications medium for communicating data between said at least one processor and said main memory; and

memory access control logic controlling access by said at least one processor to said main memory, said memory access control logic supporting a plurality of different configurations of said memory modules embodying said main memory, said memory access control logic decoding a memory address to a plurality of physical parameter selections representing physical parameters, wherein, for a plurality of said physical parameter selections, a number of such selections to which said memory address is decoded by said memory access control logic is variable depending on the memory module configuration of said plurality of configurations of memory modules;

wherein said memory access control logic decodes a first subset of said physical parameter selections from consistent bit positions of said memory address, said first subset comprising at least two physical parameter selections of said plurality of physical parameter selections for which a number of such selections to which said memory address is decoded by said memory access control logic is variable depending of the memory module configuration.

2. The digital data processing system of claim 1,

wherein said system comprises a plurality of processors;

wherein said main memory is distributed as a plurality of local memories, each local memory being associated with one or more respective processors of said plurality of processors; and

wherein said memory access control logic is distributed as a plurality of local memory controllers, each local memory controller being associated with a respective one of said plurality of local memories.

3. The digital data processing system of claim 2,

wherein each said processor generates real addresses of corresponding main memory locations to be accessed, each real address specifying a unique data location in said main memory;

and

wherein each said local memory controller translates real addresses generated by processors to corresponding local addresses, each local address specifying a unique data location in the respective local memory associated with each local memory controller, wherein at least some local addresses are duplicated in different local memories.

4. The digital data processing system of claim 3, wherein each local memory contains a portion reserved as a remote cache for caching data residing in said main memory but not in the local memory.

5. The digital data processing system of claim 1, wherein said memory access control logic supports decoding of said memory address according to a plurality of sets of decoding maps, including a first set in which a first physical parameter selection of said plurality of physical parameter selections is decoded from consistent bit positions of said memory address for a first plurality of different configurations of said memory modules, and a second set of decoding maps in which said first physical parameter selection is not decoded from consistent bit positions of said memory address for said first plurality of different configurations.

6. The digital data processing system of claim 5, wherein said memory access control logic comprises fast partial decode logic for decoding said first physical parameter selection according to said first set of decoding maps, said fast partial decode logic producing said first physical parameter selection before one or more other physical parameters are decoded from said memory address.

7. A digital data processing system, comprising:

at least one processor;

a plurality of memory modules embodying a main memory;

a communications medium for communicating data between said at least one processor and said main memory; and

memory access control logic controlling access by said at least one processor to said main memory, said memory access control logic decoding a memory address to a plurality of physical parameter selections representing physical parameters of said main memory;

wherein said memory access control logic comprises a first subset of decode logic and a second subset of decode logic, said first subset of decode logic decoding at least a portion of said memory address to a first subset of said plurality of physical parameter selections, said first subset of physical parameter selections being fewer than all of said plurality of physical parameter selections, said second subset of decode logic decoding at least a portion of said memory address to a second subset of said plurality of physical parameter selections, said first subset of decode logic producing said first subset of said plurality of physical parameter selections before said second subset of decode logic produces said second subset of said plurality of physical parameter selections.

8. The digital data processing system of claim 7,

wherein said system comprises a plurality of processors;

wherein said main memory is distributed as a plurality of local memories, each local memory being associated with one or more respective processors of said plurality of processors; and

wherein said memory access control logic is distributed as a plurality of local memory controllers, each local memory controller being associated with a respective one of said plurality of local memories.

9. The digital data processing system of claim 8,

wherein each said processor generates real addresses of corresponding main memory locations to be accessed, each real address specifying a unique data location in said main memory;

and

wherein each said local memory controller translates real addresses generated by processors to local addresses, each local address specifying a unique data location in the respective local memory associated with each local memory controller, wherein at least some local addresses are duplicated in different local memories.

10. The digital data processing system of claim 9,

wherein a first subset of address bits of each said local address is identical to a first subset of address bits of the corresponding real address from which the local address was translated;

wherein said first subset of decode logic decodes each said first subset of address bits of a respective real address to a corresponding said first subset of said plurality of physical parameter selections, each said first subset of address bits of a respective real address being input to said first subset of decode logic before the respective real address is translated to a corresponding local address; and

wherein said second subset of decode logic decodes at least a portion of said corresponding local address to said second subset of said plurality of physical parameter selections after the respective real address corresponding to said corresponding local address is translated to said corresponding local address.

11. The digital data processing system of claim 7, wherein said first subset of said plurality of physical parameter selections comprises at least one of the set consisting of:

(a) a memory port select, (b) a memory chip group select; and

(c) an internal memory bank select.

12. The digital data processing system of claim 7, wherein said memory access control logic supports decoding of said memory address according to a plurality of sets of decoding maps, including a first set in which a first physical parameter selection of said first subset of physical parameter selections is decoded from consistent bit positions of said memory address for a first plurality of different configurations of said memory modules, and a second set of decoding maps in which said first physical parameter selection is not decoded from consistent bit positions of said memory address for said first plurality of different configurations.

13. A memory controller for a digital device, comprising:

an interface for communicating with a plurality of memory modules embodying an addressable memory;

logic receiving memory addresses for processing by said digital device;

memory access logic which accesses said memory locations in said addressable memory responsive to receiving said memory addresses, said memory access logic supporting a plurality of different configurations of said memory modules embodying said addressable memory, said memory access logic decoding a memory address to a plurality of physical parameter selections representing physical parameters, wherein, for a plurality of said physical parameter selections, a number of such selections to which said memory address is decoded by said memory access logic is variable depending on the memory module configuration of said plurality of configurations of memory modules;

wherein said memory access logic decodes a first subset of said physical parameter selections from consistent bit positions of said memory address, said first subset comprising at least two physical parameter selections of said plurality of physical parameter selections for which a number of such selections to which said memory address is decoded by said memory access logic is variable depending of the memory module configuration.

14. The memory controller of claim 13,

wherein said digital device comprises a main memory which is distributed as a plurality of local memories, each local memory being accessed using a separate respective memory controller;

wherein said main memory is addressable using real addresses, each real address specifying a unique data location in said main memory; and

wherein each said memory controller translates real addresses to corresponding local addresses, each local address specifying a unique data location in the respective local memory associated with each memory controller, wherein at least some local addresses are duplicated in different local memories.

15. The memory controller of claim 13, wherein said memory access logic supports decoding of said memory address according to a plurality of sets of decoding maps, including a first set in which a first physical parameter selection of said plurality of physical parameter selections is decoded from consistent bit positions of said memory address for a first plurality of different configurations of said memory modules, and a second set of decoding maps in which said first physical parameter selection is not decoded from consistent bit positions of said memory address for said first plurality of different configurations.

16. The memory controller of claim 15, wherein said memory access logic comprises fast partial decode logic for decoding said first physical parameter selection according to said first set of decoding maps, said fast partial decode logic producing said first physical parameter selection before one or more other physical parameters are decoded from said memory address.

17. A memory controller for a digital device, comprising:

an interface for communicating with a plurality of memory modules embodying an addressable memory;

logic receiving memory addresses for processing by said digital device;

memory access logic which accesses said memory locations in said addressable memory responsive to receiving said memory addresses digital data processing system, said memory access logic decoding a memory address to a plurality of physical parameter selections representing physical parameters of said main memory, said plurality of physical parameter selections including a row select and a column select representing a row and column respectively of memory cell arrays in said memory modules embodying an addressable memory;

wherein said memory access logic produces a decoded selection of a first subset of said plurality of physical parameter selections, said first subset of physical parameter selections not including said column select, said first subset of physical parameter selections being decoded from at least a portion of said memory address, before said memory access control logic produces said column select from at least a portion of said memory address.

18. The memory controller of claim 17,

wherein said digital device comprises a main memory which is distributed as a plurality of local memories, each local memory being accessed using a separate respective memory controller;

wherein said main memory is addressable using real addresses, each real address specifying a unique data location in said main memory; and

wherein each said memory controller translates real addresses to corresponding local addresses, each local address specifying a unique data location in the respective local memory associated with each memory controller, wherein at least some local addresses are duplicated in different local memories.

19. The memory controller of claim 18,

wherein a first subset of address bits of each said local address is identical to a first subset of address bits of the corresponding real address from which the local address was translated;

wherein a first subset of decode logic decodes each said first subset of address bits of a respective real address to a corresponding said first subset of said plurality of physical parameter selections, each said first subset of address bits of a respective real address being input to said first subset of decode logic before the respective real address is translated to a corresponding local address; and

wherein a second subset of decode logic decodes at least a portion of said corresponding local address to said column select after the respective real address corresponding to said corresponding local address is translated to said corresponding local address.

20. The memory controller of claim 17, wherein said first subset of said plurality of physical parameter selections comprises at least one of the set consisting of:

(a) a memory port select, (b) a memory chip group select; and

(c) an internal memory bank select.