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Method and apparatus for a configurable protection architecture for on-chip systems

  • US 20060129747A1
  • Filed: 09/27/2005
  • Published: 06/15/2006
  • Est. Priority Date: 11/05/2002
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a target intellectual property block that fields and services requests from an initiator intellectual property block in a system-on-chip network, wherein the system-on-chip network has an associated protection mechanism with logic configured to restrict access for the requests to the target intellectual property block based on access permissions associated with a protection region within the target intellectual property block and attributes of the request trying to access that region.

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