Semiconductor memory and method of testing semiconductor memory

• US 20060129844A1
• Filed: 10/31/2005
• Published: 06/15/2006
• Est. Priority Date: 11/18/2004
• Status: Active Grant

• Current Assignee: Megachips Corporation
• Original Assignee: Megachips Corporation
• Inventors: Oshikiri, Takashi
• Granted Patent: US 8,090,958 B2
• Time in Patent Office: Days
• US Class Current: 713/190
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 2029/1806 Address conversion or mapping, i.e. logical to physical address
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/18 Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters

Abstract

A memory-specific tester has a buffer storing input pattern data and output expectation data. An address included in the input pattern data read from the buffer is sent to a semiconductor memory, and is then subjected to descrambling at a security circuit. The descrambled address is converted at an address conversion circuit to an address designating a region for storing a check pattern in a memory core. Data given from the memory core (check pattern) is subjected to scrambling at the security circuit, and is then sent to the memory-specific tester. The memory-specific tester makes comparison between expectation data and the data read from the semiconductor memory.

Claims

1. A semiconductor memory, comprising:

an address conversion circuit configured to convert an address with no security protection to an address designating a predetermined storage region;

a memory core having said predetermined storage region storing a check pattern; and

a security processing circuit including at least a security release circuit or a security protection circuit, said security release circuit being configured to release an address subjected to first security protection from said first security protection, said security protection circuit being configured to provide second security protection to data sent from said memory core.

2. The semiconductor memory according to claim 1,

wherein said check pattern is independent of data stored in a region in said memory core other than said predetermined storage region.

3. The semiconductor memory according to claim 1,

wherein said security processing circuit includes said security release circuit, said semiconductor memory further comprising:

a first path configured to allow an address received at said semiconductor memory to bypass said security processing circuit; and

a second path configured to allow an address received at said semiconductor memory to bypass said address conversion circuit.

4. The semiconductor memory according to claim 3,

wherein said security processing circuit includes said security protection circuit,

said semiconductor memory further comprising

a third path configured to allow said data sent from said memory core to bypass said security processing circuit.

5. The semiconductor memory according to claim 1, wherein said security processing circuit includes said security protection circuit,

said semiconductor memory further comprising

a path configured to allow said data sent from said memory core to bypass said security processing circuit.

6. A method of testing the semiconductor memory as recited in claim 3, comprising the steps of:

providing input pattern data subjected to said first security protection to said security release circuit to obtain said address with no security protection;

sending said address with no security protection from said security release circuit to said address conversion circuit to obtain an address designating said predetermined storage region;

providing said address designating said predetermined storage region to said memory core to obtain said check pattern; and

making comparison between data given from said semiconductor memory based on said check pattern and an expectation of said data.

7. A method of testing the semiconductor memory as recited in claim 5, comprising the steps of:

providing said address with no security protection to said address conversion circuit to obtain an address designating said predetermined storage region;

providing said address designating said predetermined storage region to said memory core to obtain said check pattern;

providing said check pattern to said security protection circuit to provide said second security protection to said check pattern; and

making comparison between data given from said security protection circuit and an expectation of said data.