Compiling method, apparatus, and program
First Claim
1. ) An information processing apparatus having a plurality of central processors, comprising:
- a temperature measuring section for measuring the temperature of each central processor of the plurality of central processors;
a halt percentage calculating section for calculating a halt percentage for said each central processor from the measured temperature of said each central processor, the halt percentage being a percentage of time in which processing by said each central processor is to be being halted to the time in which electric power is being supplied to at least a part of said each central processor;
a halt state control section implemented by a particular thread associated with said each central processor and executed in said each central processor, the halt state control section transitioning to a wait state in which the halt control section causes said each central processor to execute another thread during a predetermined wait period or a running state in which the halt control section executes an internal halt instruction to cause said each central processor to halt processing, thereby causing said each central processor to halt processing in accordance with the halt percentage;
an interrupting section for interrupting said each central processor and causing any central processor that is halting processing to resume processing.
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Accused Products
Abstract
Provides flexible control of power consumption of central processors. An apparatus has central processors, including: section for measuring temperature of each central processor; section for calculating halt percentage for each of the central processors from measured temperature of central processor, halt percentage being percentage of time in which processing by the central processor is to be being halted; halt state control section implemented by a particular thread executed in each of the central processors, halt state control section transitioning to await state in which the halt control section causes central processor to execute another thread during predetermined wait period or a running state in which the halt control executes an internal halt instruction causing the central processor to halt processing in accordance with the halt percentage; an section for interrupting each of the central processors and causing a central processor that is halting processing to resume processing.
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Citations
20 Claims
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1. ) An information processing apparatus having a plurality of central processors, comprising:
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a temperature measuring section for measuring the temperature of each central processor of the plurality of central processors;
a halt percentage calculating section for calculating a halt percentage for said each central processor from the measured temperature of said each central processor, the halt percentage being a percentage of time in which processing by said each central processor is to be being halted to the time in which electric power is being supplied to at least a part of said each central processor;
a halt state control section implemented by a particular thread associated with said each central processor and executed in said each central processor, the halt state control section transitioning to a wait state in which the halt control section causes said each central processor to execute another thread during a predetermined wait period or a running state in which the halt control section executes an internal halt instruction to cause said each central processor to halt processing, thereby causing said each central processor to halt processing in accordance with the halt percentage;
an interrupting section for interrupting said each central processor and causing any central processor that is halting processing to resume processing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 17, 20)
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11. ) A control method, in an information processing apparatus having a plurality of central processors, for controlling the power consumption of the plurality of central processors, the method comprising:
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a temperature measuring step of measuring the temperature of each central processor of the plurality of central processors;
a halt percentage calculating step of calculating a halt percentage for each of the plurality of central processors from the measured temperature of said each central processor, the halt percentage being the percentage of time in which processing by said each central processor is to be being halted to the time in which electric power is being supplied to at least a part of said each central processor;
a halt state control step, implemented by a particular thread associated with each of the plurality of central processors and executed in the central processor, of transitioning to a wait state in which the halt control section causes the central processor to execute another thread during predetermined wait period or a running state in which the halt control section executes an internal halt instruction to cause said each central processor to halt processing, thereby causing said each central processor to halt processing in accordance with the halt percentage; and
an interrupting step of interrupting each of the plurality of central processors and causing a central processor that is halting processing to resume processing. - View Dependent Claims (13, 18, 19)
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15. ) A program for controlling an information processing apparatus having a plurality of central processors, the program causing the information processing apparatus to function as:
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a temperature measuring section for measuring the temperature of each of the plurality of central processors;
a halt percentage calculating section for calculating a halt percentage for each of the central processors from the measured temperature of the central processor, the halt percentage being the percentage of time in which processing by the central processor is to be being halted to the time in which electric power is being supplied to at least a part of the central processor;
a halt state control section implemented by a particular thread associated with each of the plurality of central processors and executed in the central processor, the halt state control section transitioning to a wait state in which the halt control section causes the central processor to execute another thread during predetermined wait period or a running state in which the halt control section executes an internal halt instruction to cause the central processor to halt processing, thereby causing the central processor to halt processing in accordance with the halt percentage;
an interrupting section for interrupting each of the plurality of central processors and causing a central processor that is halting processing to resume processing. - View Dependent Claims (16)
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Specification