Isolation circuit

• US 20060131577A1
• Filed: 01/24/2006
• Published: 06/22/2006
• Est. Priority Date: 06/20/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cowles, Timothy B., Lunde, Aron T.
• Granted Patent: US 7,550,762 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.

Claims

1. An isolation circuit, comprising:

a wireless identification circuit;

a first pad adapted to receive a test signal;

a second pad coupled to a microelectronic die; and

a first device adapted to transfer the test signal from the first pad to the second pad in response to a signal from the wireless identification circuit.

2. The isolation circuit of claim 1, further comprising a second device to selectively inactivate the first device during a predetermined use of the microelectronic die.

3. The isolation circuit of claim 2, wherein the first device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper and a wireless identification circuit.

4. The isolation circuit of claim 3, wherein the second device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper and a wireless identification circuit.

5. The isolation circuit of claim 1, wherein the first pad is located in a scribe area of a substrate.

6. The isolation circuit of claim 5, wherein the second pad is located in a scribe area of a substrate.

7. The isolation circuit of claim 6, wherein the wireless identification circuit is positioned in a redistribution layer.

16. The microelectronic die of claim 1, wherein the first pad is located adjacent a scribe area of a substrate.

17. The microelectronic die of claim 5, wherein the second pad is located adjacent a scribe area of a substrate.

18. The microelectronic die of claim 17, wherein the wireless identification circuit is positioned in a redistribution layer.

8. An isolation circuit, comprising:

a first pad to receive a signal;

a second pad coupled to a microelectronic die;

a first device adapted to transfer the signal from the first pad to the second pad in response to a control signal; and

a second device to selectively prevent the first pad from being coupled to the second pad.

9. The isolation circuit of claim 8, further comprising a wireless identification circuit to provide the control signal.

10. The isolation circuit of claim 8, further comprising a control pad to receive the control signal.

11. The isolation circuit of claim 8, wherein the first device comprises a metal oxide semiconductor (MOS) transistor adapted to transfer a test signal from the second pad in response to a predetermined control signal.

12. The isolation circuit of claim 8, wherein the second device comprises a wireless identification circuit.

13. A microelectronic die, comprising:

a first pad to receive a test signal during testing of at least one component formed on the microelectronic die;

a second pad coupled to the at least one component;

a first device adapted to transfer the test signal from the first pad to the second pad in response to a control signal; and

a second device to selectively prevent the first pad from being coupled to the second pad during a predetermined use of the microelectronic die.

14. The microelectronic die of claim 13, wherein the first device comprises an N-channel transistor and the second device inactivates the N-channel transistor by coupling a gate of the N-channel transistor to ground potential.

15. The microelectronic die of claim 13, wherein the first device comprises a P-channel transistor and the second device inactivates the P-channel transistor by coupling a gate of the P-channel transistor to a high potential.

19. A semiconductor wafer, comprising:

a plurality of microelectronic dies; and

at least one isolation circuit associated with each microelectronic die, the at least one isolation circuit including;

a first pad to receive a test signal during testing of the associated microelectronic die;

a second pad coupled to the associated microelectronic die;

a first device adapted to transfer the test signal from the first pad to the second pad in response to a control signal; and

a second device to selectively prevent the first pad from being coupled to the second pad a predetermined use of the microelectronic die.

20. The semiconductor wafer of claim 19, further comprising a redistribution layer, wherein the first and second pads are formed in the redistribution layer.

21. The semiconductor wafer of claim 19, wherein the first pad is located adjacent a scribe area of a substrate.

22. The microelectronic die of claim 21, wherein the second pad is located adjacent a scribe area of a substrate.

23. An electronic system, comprising:

a processor; and

a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including an isolation circuit, the isolation circuit including;

a first pad to receive a test signal during testing of the system;

a second pad coupled to the at least one of the processor and the memory system;

a first device adapted to transfer the test signal from the first pad to the second pad in response to a control signal; and

a second device to selectively prevent the first pad from being coupled to the second pad during normal operations of the electronic system.

24. The electronic system of claim 23, wherein the first device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper, a wireless identification circuit and a fuse device.

25. The electronic system of claim 23, wherein the second device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper, a wireless identification circuit and a fuse device.