Isolation circuit
First Claim
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1. An isolation circuit, comprising:
- a wireless identification circuit;
a first pad adapted to receive a test signal;
a second pad coupled to a microelectronic die; and
a first device adapted to transfer the test signal from the first pad to the second pad in response to a signal from the wireless identification circuit.
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Abstract
An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.
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Citations
25 Claims
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1. An isolation circuit, comprising:
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a wireless identification circuit;
a first pad adapted to receive a test signal;
a second pad coupled to a microelectronic die; and
a first device adapted to transfer the test signal from the first pad to the second pad in response to a signal from the wireless identification circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 16, 17, 18)
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8. An isolation circuit, comprising:
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a first pad to receive a signal;
a second pad coupled to a microelectronic die;
a first device adapted to transfer the signal from the first pad to the second pad in response to a control signal; and
a second device to selectively prevent the first pad from being coupled to the second pad. - View Dependent Claims (9, 10, 11, 12)
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13. A microelectronic die, comprising:
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a first pad to receive a test signal during testing of at least one component formed on the microelectronic die;
a second pad coupled to the at least one component;
a first device adapted to transfer the test signal from the first pad to the second pad in response to a control signal; and
a second device to selectively prevent the first pad from being coupled to the second pad during a predetermined use of the microelectronic die. - View Dependent Claims (14, 15)
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19. A semiconductor wafer, comprising:
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a plurality of microelectronic dies; and
at least one isolation circuit associated with each microelectronic die, the at least one isolation circuit including;
a first pad to receive a test signal during testing of the associated microelectronic die;
a second pad coupled to the associated microelectronic die;
a first device adapted to transfer the test signal from the first pad to the second pad in response to a control signal; and
a second device to selectively prevent the first pad from being coupled to the second pad a predetermined use of the microelectronic die. - View Dependent Claims (20, 21, 22)
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23. An electronic system, comprising:
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a processor; and
a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including an isolation circuit, the isolation circuit including;
a first pad to receive a test signal during testing of the system;
a second pad coupled to the at least one of the processor and the memory system;
a first device adapted to transfer the test signal from the first pad to the second pad in response to a control signal; and
a second device to selectively prevent the first pad from being coupled to the second pad during normal operations of the electronic system. - View Dependent Claims (24, 25)
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Specification