Semiconductor device and method of manufacturing the same

• US 20060131641A1
• Filed: 01/25/2006
• Published: 06/22/2006
• Est. Priority Date: 05/27/2003
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozawa, Yoshio, Takeuchi, Yuji, Saida, Shigehiko, Saito, Masanobu
• Granted Patent: US 7,612,401 B2
• Time in Patent Office: Days
• US Class Current: 257/321
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

Claims

1. A semiconductor device comprising:

a semiconductor substrate; and

a non-volatile memory cell provided on the semiconductor substrate,

the non-volatile memory cell comprising;

a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell;

a floating gate electrode provided on the tunnel insulating film;

a control gate electrode provided above the floating gate electrode; and

an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

2. The semiconductor device according to claim 1,

wherein a height of an interface between the tunnel insulating film and the semiconductor substrate periodically and continuously changes in the channel width direction.

3. The semiconductor device according to claim 2,

wherein an upper surface of the tunnel insulating film is nearly flat.

4. A semiconductor device comprising:

a semiconductor substrate; and

a non-volatile memory cell provided on the semiconductor substrate,

the non-volatile memory cell comprising;

a tunnel insulating film having an approximately constant film thickness, a height of an interface between the tunnel insulating film and the semiconductor substrate periodically and continuously changing in a channel width direction of the non-volatile memory cell;

a floating gate electrode provided on the tunnel insulating film, a height of an interface between the floating gate electrode and the tunnel insulating film periodically and continuously changing in the channel width direction of the non-volatile memory cell;

a control gate electrode above the floating gate electrode; and

an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

5-20. -20. (canceled)