Semiconductor device and manufacturing method thereof

• US 20060131645A1
• Filed: 11/14/2005
• Published: 06/22/2006
• Est. Priority Date: 11/15/2004
• Status: Abandoned Application

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Kaneko, Mamoru
• Application Number:
  US11/272,482
• Publication Number:
  US 20060131645A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In the present invention, an npn junction or a pin junction is formed in an element peripheral part surrounding an element part. In addition, the same potential as that of a source electrode in the element part is applied, and a breakdown voltage of the element peripheral part is set to be always lower than that of the element part. Alternatively, resistance of the element peripheral part is lowered. Thus, breakdown always occurs in the element peripheral part, and the breakdown voltage becomes stable. Moreover, damage caused by breakdown can be prevented by eliminating occurrence of breakdown in a fragile gate oxide film. Furthermore, since the resistance is lowered, electrostatic breakdown strength is improved.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

an element part that is part of the substrate and comprises a plurality of trench-type transistors, each of the transistors comprising a vertical cannel disposed between a source region formed in a surface of the substrate and a drain region that is disposed below the source region in the substrate;

an element peripheral part that is part of the substrate and surrounds the element part;

a peripheral impurity region that is disposed in the element peripheral part and has a same general conductivity type as the channel; and

an electrode that is disposed on the peripheral impurity region and is electrically connected to the source regions.

2. The semiconductor device of claim 1, further comprising a contact impurity region that has a same general conductivity type as the source regions and is disposed between the electrode and the peripheral impurity region.

3. The semiconductor device of claim 1, wherein an impurity concentration of the peripheral impurity region is determined so that under application of a voltage between the source and drain regions a breakdown occurs at the element peripheral part.

4. The semiconductor device of claim 1, wherein an impurity concentration of the peripheral impurity region is determined so that a breakdown voltage of the element peripheral part is lower than a breakdown voltage of the element part.

5. The semiconductor device of claim 1, wherein an impurity concentration of the peripheral impurity region is approximately equal to an impurity concentration of the channel.

6. The semiconductor device of claim 1, further comprising an additional impurity region that is disposed in the peripheral impurity region, has an impurity concentration lower than an impurity concentration of the peripheral impurity region and has the same general conductivity type as the channel.

7. The semiconductor device of claim 1, further comprising an additional impurity region that is disposed in the peripheral impurity region, has an impurity concentration higher than an impurity concentration of the peripheral impurity region and has the same general conductivity type as the channel.

8. The semiconductor device of claim 2, wherein an impurity concentration of the contact impurity region is approximately equal to an impurity concentration of the source region.

9. The semiconductor device of claim 1, wherein a resistance of the element peripheral part is lower than a resistance of the element part.

10. The semiconductor device of claim 1, further comprising an additional impurity region that is disposed in the peripheral impurity region, has an impurity concentration higher than an impurity concentration of the peripheral impurity region, has the same general conductivity type as the channel and is deeper than the peripheral impurity region.

11. The semiconductor device of claim 1, wherein an impurity concentration of the peripheral impurity region is higher than an impurity concentration of the channel, and the peripheral impurity region is deeper than the channel layer.

12. The semiconductor device of claim 1, wherein the element part comprises a guard ring that has the same general conductivity type as the channel and is disposed at an edge portion of the element part.

13. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate of a first general conductivity type;

defining an element part of the substrate in which a plurality of transistors are formed;

forming an impurity region of a second general conductivity type in the substrate around the element part; and

forming a peripheral electrode that is disposed on the impurity region and connected to electrodes of the transistors.

14. The method of claim 13, further comprising forming a contact impurity region that is disposed between the peripheral electrode and the impurity region.

15. The method of claim 13, further comprising forming a channel layer on the substrate, forming trenches in the channel layer, filling the trenches with a conducting material and forming source regions in the surface of the substrate so that the transistors are made.

16. The method of claim 13, further comprising forming an additional impurity region of the second general conductivity type in the impurity region so as to have an impurity concentration lower than the impurity region.

17. The method of claim 13, further comprising forming an additional impurity region of the second general conductivity type in the impurity region so as to have an impurity concentration higher than the impurity region.

18. The method of claim 13, wherein an impurity concentration of the impurity region is determined so that a breakdown voltage of the impurity region is lower than a breakdown voltage of the element part.

19. The method of claim 13, further comprising forming an additional impurity region of the second general conductivity type in the impurity region so as to have an impurity concentration higher than the impurity region and to have a depth larger than the impurity region.

20. The method of claim 15, wherein the formation of the channel layer is such that an impurity concentration of the impurity region is higher than an impurity concentrations of the channel layer and a depth of the impurity region is larger than the channel layer.

21. The method of claim 13, wherein the formation of the impurity region is such that a resistance of the impurity region is lower than a resistance of the element part.

22. The method of claim 15, wherein the impurity region and the channel layer are formed in a same process step.