MOS device, CMOS device, and fabricating method thereof

• US 20060131658A1
• Filed: 12/22/2005
• Published: 06/22/2006
• Est. Priority Date: 12/22/2004
• Status: Abandoned Application

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: Dongbuanam Semiconductor, Inc. (DB HiTek Co., Ltd.)
• Inventors: Jong, Shin Eun
• Application Number:
  US11/313,649
• Publication Number:
  US 20060131658A1
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

A MOS or CMOS device includes a substrate with an active area, a gate oxide layer on the substrate, a gate on the gate oxide layer, first sidewalls on sides of the gate, the first sidewalls contacting the gate oxide layer, spacers formed outside the second sidewalls, and a salicide layer formed by depositing a metal layer on the gate and the active area of the substrate and annealing the deposited metal layer.

Claims

1. A metal oxide semiconductor (MOS) device comprising:

a substrate having an active area;

a gate oxide layer on the substrate;

a gate on the gate oxide layer;

first sidewalls on sides of the gate, the first sidewalls contacting the gate oxide layer;

spacers outside the first sidewalls; and

a salicide layer on the gate and the active area of the substrate.

2. The MOS device according to claim 1, wherein the gate oxide layer includes a first gate oxide layer having a thickness of 45-55 Å

and a second gate oxide layer having a thickness of 20-30 Å

.

3. The MOS device according to claim 1, wherein the gate comprises polysilicon having a thickness of 4500-6000 Å

.

4. The MOS device according to claim 1, wherein the salicide layer is formed by depositing a metal layer on the gate and the active area of the substrate and annealing the deposited metal layer.

5. The MOS device according to claim 4, wherein the metal layer comprises Ti having a deposited thickness of 300-400 Å

.

6. The MOS device according to claim 1, wherein the gate comprises an upper portion having a first width and a lower portion having a second width, the first width being greater than the second width.

7. The MOS device according to claim 1, wherein the MOS device has a 0.25-μ

m design rule or less.

8. The MOS device according to claim 1, wherein the salicide layer comprises Ti silicide, and the MOS device further comprises a TiN layer on the Ti silicide, the TiN layer having a thickness of 100-200 Å

.

9. A complementary metal oxide semiconductor (CMOS) device comprising an NMOS element and a PMOS element, each of the NMOS element and the PMOS element including:

a substrate having an active area;

a gate oxide layer on the substrate;

a gate on the gate oxide layer;

first sidewalls on sides of the gate, the first sidewalls contacting the gate oxide;

spacers outside the first sidewalls; and

a salicide layer on the gate and the active area of the substrate.

10. The CMOS device according to claim 9, wherein the gate comprises polysilicon having a thickness of 4500-6000 Å

.

11. The CMOS device according to claim 9, wherein the salicide layer comprises Ti silicide, and the CMOS device further comprises a TiN layer on the Ti silicide, the TiN layer having a thickness of 100-200 Å

.

12. The CMOS device according to claim 9, wherein the gate comprises an upper portion having a first width and a lower portion having a second width, the first width being greater than the second width.

13. The CMOS device according to claim 9, wherein the CMOS device has a 0.25-μ

m design rule or less.

14. A method of fabricating a complementary metal oxide semiconductor (CMOS) device, comprising:

patterning a first insulating layer on a substrate to expose a portion of the substrate;

forming a gate insulating layer on the exposed portion of the substrate;

depositing a gate material on the gate insulating layer and planarizing the deposited gate material;

patterning the gate material and the first insulating layer at a predetermined width to thereby form a gate and first sidewalls, respectively;

forming spacers from a second insulating layer on the substrate, adjacent to the first sidewalls;

forming source and drain regions by implanting first impurity ions into the substrate adjacent to the spacers;

depositing a metal layer on the gate and the substrate; and

annealing the metal layer to form a salicide.

15. The method according to claim 14, further comprising, after patterning the gate material and the first insulating layer, forming a lightly doped drain (LDD) region by implanting second impurity ions into the substrate and performing a thermal treatment.

16. The method according to claim 14, wherein forming the gate insulating layer includes forming first and second gate oxide layers having respective thicknesses of 45-55 Å

and 20-30 Å

through a dual or differential oxidation process.

17. The method according to claim 14, wherein depositing the gate material includes depositing a layer of polysilicon to a thickness of 4500-6000 Å

.

18. The method according to claim 14, wherein depositing the metal layer comprises depositing Ti to a thickness of 300-400 Å

.

19. The method according to claim 18, further comprising forming a layer of TiN having a thickness of 100-200 Å

on the salicide.

20. The method according to claim 14, wherein annealing the metal layer includes:

performing a first thermal treatment on the substrate;

cleaning the substrate to remove a remaining metal layer; and

performing a second thermal treatment on the substrate.

21. The method according to claim 20, wherein the first thermal treatment comprises a rapid thermal process (RTP) performed at 600-800°

C., for 10-50 seconds in a nitrogen atmosphere.

22. The method according to claim 20, wherein cleaning the substrate comprises wet etching using a solution comprising aqueous H₂SO₄ and aqueous H₂O₂ mixed in a ratio of from 1:

1 to 1;

3.

23. The method according to claim 20, wherein the second thermal treatment comprises annealing, performed at 700-900°

C. for 10-30 seconds in a nitrogen atmosphere.