Nitrogen treatment to improve high-k gate dielectrics
First Claim
1. A gate dielectric for use in a transistor comprising:
- a nitrogen-containing, high-k dielectric layer; and
an underlying dielectric layer, the underlying dielectric layer having a nitrogen-containing first portion in contact with the high-k dielectric layer, and a substantially nitrogen-free second portion in contact with an underlying substrate.
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Abstract
A MOSFET having a nitrided gate dielectric and its manufacture are disclosed. The method comprises providing a substrate and depositing a non-high-k dielectric material on the substrate. The non-high-k dielectric comprises two layers. The first layer adjacent the substrate is essentially nitrogen-free, and the second layer includes between about 1015 atoms/cm3 to about 1022 atoms/cm3 nitrogen. The MOSFET further includes a high-k dielectric material on the nitrided, non-high-k dielectric. The high-k dielectric preferably includes HfSiON, ZrSiON, or nitrided Al2O3. Embodiments further include asymmetric manufacturing techniques wherein core and peripheral integrated circuit areas are separately optimized.
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Citations
23 Claims
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1. A gate dielectric for use in a transistor comprising:
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a nitrogen-containing, high-k dielectric layer; and
an underlying dielectric layer, the underlying dielectric layer having a nitrogen-containing first portion in contact with the high-k dielectric layer, and a substantially nitrogen-free second portion in contact with an underlying substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A transistor comprising:
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a substrate;
a gate structure comprising, a first dielectric layer on the substrate, the first dielectric layer having a substantially nitrogen-free region adjacent the substrate and a nitrogen-containing region adjacent the nitrogen-free region, a nitrogen-containing, high-k dielectric layer on the first dielectric layer, and a gate electrode on a second dielectric layer, a source region and a drain region adjacent and on opposed sides, respectively, of the gate structure and defining there between a channel region, the channel region having a length of less than about 100 nm. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A semiconductor device having a core region and an input/output (I/O) region on a substrate, the semiconductor device comprising:
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an underlying dielectric layer on the substrate, the underlying dielectric layer having a first thickness over the I/O region and a second thickness over the core region, wherein the first thickness is greater than the second thickness;
a high-k dielectric layer on the underlying dielectric layer over the I/O region and the core region, wherein the underlying dielectric layer over the I/O region is partially nitrided, and the underlying dielectric layer over the core region is fully nitrided. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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Specification