Mock wafer, system calibrated using mock wafer, and method for calibrating automated test equipment

• US 20060132162A1
• Filed: 12/16/2004
• Published: 06/22/2006
• Est. Priority Date: 12/16/2004
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Verigy Limited (Advantest Corporation)
• Inventors: Mayder, Romi
• Granted Patent: US 7,323,897 B2
• Time in Patent Office: Days
• US Class Current: 324/750.20
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 35/005 Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references G01R33/0035, G01R35/002 take precedence

Abstract

In one embodiment, a mock wafer for calibrating automated test equipment includes a printed circuit board having a number of interconnect areas, with each interconnect area having a pair of mock die pads that are coupled via a connecting trace. In another embodiment, a method for calibrating automated test equipment (ATE) may include coupling the mock wafer to the ATE, and then causing the ATE to i) index the mock wafer with respect to a test head connector, ii) couple a number of probes or the test head connector to a number of the mock wafer'"'"'s mock die pads, iii) transmit a test signal between a pair of the probes that are coupled via a pair of mock die pads and connecting trace of the mock wafer, and iv) calibrate a selected signal path or paths of the ATE by recording a characteristic of the transmitted test signal.

Claims

1. A mock wafer for calibrating automated test equipment, the mock wafer comprising:

a printed circuit board having a number of interconnect areas, with each interconnect area comprising a pair of mock die pads that are coupled via a connecting trace.

2. The mock wafer of claim 1, wherein the mock die pads of each pair have a relationship that corresponds to a relationship between a pair of production die pads.

3. The mock wafer of claim 1, wherein the printed circuit board has a plurality of said interconnect areas, each of which comprises a unique pair of connected mock die pads.

4. The mock wafer of claim 3, wherein each unique pair of connected mock die comprises i) a first mock die pad corresponding to a single production die pad, and ii) a second mock die pad corresponding to a unique other production die pad.

5. The mock wafer of claim 1, wherein each interconnect area comprises a set of mock die pads equal in number to a set of die pads on a production die.

6. The mock wafer of claim 1, wherein the printed circuit board has a number of said interconnect areas equal to a number of die pads on a production die, less a number of reference, ground and power pads on said production die.

7. The mock wafer of claim 1, wherein the printed circuit board comprises only two metal layers, separated by a dielectric layer.

8. The mock wafer of claim 7, wherein thicknesses of the metal and dielectric layers are chosen to provide a fifty ohm (50Ω

) impedance for traces formed in one of the metal layers.

9. The mock wafer of claim 8, wherein there are no conductive paths coupling the two metal layers.

10. The mock wafer of claim 1, wherein heights of the mock die pads on said printed circuit board substantially match heights of production die pads on a production wafer.

11. The mock wafer of claim 1, wherein the mock die pads are plated with nickel and hard gold.

12. A system, comprising:

automated test equipment (ATE) comprising i) a processor, and ii) a test head connector that is coupled to a plurality of signal paths of the ATE;

a mock wafer comprising a printed circuit board (PCB) having a number of interconnect areas, with each interconnect area comprising a pair of mock die pads that are coupled via a connecting trace; and

a calibration program, executed by the processor, that causes the ATE to i) index the mock wafer with respect to the test head connector, ii) couple a number of probes of the test head connector to a number of the mock wafer'"'"'s die pads, iii) transmit a test signal between a pair of the probes that are coupled via a pair of mock die pads and connecting trace of the mock wafer, and iv) calibrate a selected signal path or paths of the ATE by recording a characteristic of the transmitted test signal.

13. The system of claim 12, wherein the test head connector comprises a probecard.

14. The system of claim 12, wherein the calibration program causes the ATE to repeat said indexing, coupling, test signal transmission and calibration;

and wherein each repetition is associated with a different indexing of the mock wafer and test head connector.

15. The system of claim 14, wherein each of said pairs of mock die pads comprise a mock die pad positioned to be coupled to a reference channel of the ATE.

16. The system of claim 12, further comprising a number of additional mock wafers, each comprising a PCB having a number of interconnect areas comprising a pair of mock die pads that are coupled via a connecting trace;

wherein each of the additional mock wafers has a pattern of interconnect areas that differs from the pattern of interconnect areas of other ones of the mock wafers.

17. A method for calibrating automated test equipment (ATE), comprising:

coupling a mock wafer into the ATE, the mock wafer comprising a printed circuit board (PCB) having a number of interconnect areas, with each interconnect area comprising a pair of mock die pads that are coupled via a connecting trace; and

causing the ATE to i) index the mock wafer with respect to a test head connector, ii) couple a number of probes of the test head connector to a number of the mock wafer'"'"'s mock die pads, iii) transmit a test signal between a pair of the probes that are coupled via a pair of mock die pads and connecting trace of the mock wafer, and iv) calibrate a selected signal path or paths of the ATE by recording a characteristic of the transmitted test signal.

18. The method of claim 17, wherein recording a characteristic of the transmitted signal comprises recording a transmission delay of the test signal.

19. The method of claim 17, further comprising, causing the ATE to repeat said indexing, test signal transmission and calibration;

wherein each repetition is associated with a different indexing of the mock wafer and test head connector.