Contactless wafer level burn-in

• US 20060132167A1
• Filed: 12/22/2004
• Published: 06/22/2006
• Est. Priority Date: 12/22/2004
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Chen, Jian
• Application Number:
  US11/021,688
• Publication Number:
  US 20060132167A1
• Time in Patent Office: Days
• US Class Current: 324/750.50
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2862 Chambers or ovens; Tanks
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/1206 Location of test circuitry on chip or wafer
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/06 Acceleration testing

Abstract

A method and apparatus for performing a wafer-level burn-in. The method comprises the steps of providing the wafer into a burn-in chamber; and outputting a power and a test initiation signal to a wafer via a wireless signal. The apparatus includes a test chamber, a transport mechanism in the test chamber, a temperature control apparatus in the test chamber, and an RF transponder in the chamber.

Claims

1. A method for performing a wafer-level test sequence, comprising:

providing the wafer into a test chamber; and

outputting a power and a test initiation signal to a wafer via a wireless signal.

2. The method of claim 1 wherein the test is a burn-in test.

3. The method of claim 1 wherein the step of providing includes providing a plurality of wafers into the test chamber, and said step of outputting including outputting to said plurality of wafers.

4. The method of claim 1 wherein said step of outputting includes outputting a signal initiating a device stress test sequence on the wafer.

5. The method of claim 1.0 wherein the signal is a test enable signal.

6. The method of claim 4 wherein the step of outputting includes encoding the test initiation signal.

7. The method of claim 4 where the signal includes instructions to provide voltages to specific elements on the wafer.

8. The method of claim 1 wherein the step of outputting comprises generating an RF signal in the chamber.

9. The method of claim 1 wherein the method further includes heating the wafer in the chamber.

10. The method of claim 1 wherein the method further includes providing a built-in burn-in test circuit on the wafer coupled to devices provided on the wafer.

11. A method for providing a built-in test process, comprising:

providing a built-in test circuit on the wafer; and

providing an RF interface on the wafer coupled to the built-in test circuit.

12. The method of claim 11 wherein the step of providing a built-in test circuit on the wafer includes providing a power extraction component and a demodulator.

13. The method of claim 12 wherein the power extractor is a full wave rectifier.

14. The method of claim 12 wherein the demodulator includes in interface with the built-in test circuit to provide a control signal to the built-in test circuit.

15. The method of claim 14 wherein the demodulator provides an enable control signal.

16. The method of claim 14 wherein the demodulator decodes an encoded enable control signal.

17. The method of claim 11 wherein the step of providing a built-in test circuit includes providing at least one BIST circuit in a test circuit area of the wafer.

18. The method of claim 11 wherein the step of providing a built-in test circuit includes providing at least one BIST circuit in a die area of the wafer.

19. The method of claim 11 wherein the step of providing a built-in test circuit includes providing at least one BIST circuit in a device subject to burn-in within a die circuit area of the wafer.

20. The method of claim 11 wherein the method further includes the step of conducting a burn-in self test of at least one device on the wafer responsive to a signal provided to the RF interface.

21. The method of claim 20 wherein the step of conducting a burn-in self test includes stressing elements of a device under at least a first set of voltage conditions.

22. The method of claim 21 wherein the step of conducting a burn-in self test includes stressing said elements under at least a second set of voltage conditions.

23. The method of claim 11 further including the step of providing an at least one antenna on the wafer.

24. The method of claim 23 further including the step of providing a plurality of antennae on the wafer.

25. The method of claim 23 wherein the step of providing a plurality of antennae on the wafer includes providing at least one antenna for each semiconductor device manufactured in a die on the wafer.

26. A semiconductor wafer, comprising:

at lease one built-in test control circuit coupled to a device on the wafer; and

an RF interface coupled to provide power and a data signal to the BIST circuit.

27. The apparatus of claim 26 wherein a plurality of devices are provided in the wafer and wherein a built-in test control circuit is provided for each device on the wafer.

28. The apparatus of claim 27 wherein each test control circuit is incorporated into said device.

29. The apparatus of claim 27 wherein each test control circuit is provided in a test circuit area of the wafer and coupled to at least one of said plurality of devices by a connector.

30. The apparatus of claim 26 wherein a plurality of devices are provided on the wafer and wherein said at least one built-in test control circuit is provided in a test circuit area of the wafer and connected to at least one device by a conductor.

31. The apparatus of claim 26 further including an antenna coupled to said RF interface.

32. The apparatus of claim 31 wherein a plurality of devices are provided on the wafer and at least one antenna is associated with each of said plurality of devices.

33. The apparatus of claim 32 wherein at least one of said antennae is provided in a scribe line surrounding said die.

34. The apparatus of claim 26 wherein the RF interface includes a power rectifier.

35. The apparatus of claim 26 wherein the RF interface includes a demodulator.

36. The apparatus of claim 26 wherein each built in test control circuit includes at least one pre-defined stress condition.

37. The apparatus of claim 36 wherein each BIST includes a plurality of pre-defined stress conditions.

38. The apparatus of claim 36 wherein the pre-defined stress condition is enabled by a data signal provided to the RF interface.

39. A semiconductor wafer, including a plurality of dies, each die separated by a scribe line, comprising:

at least on RF interface circuit provided on the wafer;

at least one scribe line RF antenna coupled to the at least one RF interface circuit; and

at least one burn-in voltage control circuit coupled to the RF interface.

40. The wafer of claim 39 wherein the RF interface includes a power rectifier and a demodulator.

41. The wafer of claim 40 wherein power fro the BIST circuit is provided by the power rectifier.

42. The wafer of claim 39 wherein a plurality of scribe line antennas are provided, one associated with each of said plurality of dies.

43. The wafer of claim 42 wherein each die includes a device, and one of said plurality of scribe line antennas is associated with each die.

44. The wafer of claim 39 wherein wafer includes a plurality of RF interfaces each associated with one of said plurality of scribe line antennas.

45. The wafer of claim 44 further including a plurality of burn-in voltage control circuits, each associated with one of said devices in said die.

46. The wafer of claim 39 wherein each burn-in voltage control circuit includes a predefined stress mode for an associate device in one of said die.

47. A built-in self test circuit provided on a semiconductor wafer die, comprising:

a device interface outputting voltage controls to induce a stress in selected components of a device; and

an RF interface including a power rectifier and a signal demodulator.

48. The circuit of claim 47 wherein a plurality of dies are provided in the wafer and wherein a built-in stress control circuit is provided for each die on the wafer.

49. The circuit of claim 48 wherein each control circuit is incorporated into said device.

50. The circuit of claim 47 further including an antenna coupled to said RF interface.

51. The circuit of claim 50 wherein said antenna is formed in a series of metal layers in a scribe line surrounding said die.

52. The apparatus of claim 47 wherein each built-in self test circuit includes at least one pre-defined stress condition.

53. An apparatus for burn-in self testing, comprising:

a test chamber;

a transport mechanism in the test chamber;

a temperature control apparatus in the test chamber; and

an RF transponder in the chamber.

54. The apparatus of claim 53 further including a test controller coupled to at least the temperature control apparatus and the RF transponder.

55. The apparatus of claim 54 wherein the test controller includes instructions generating an RF signal output by said transponder to provide a power and test control signal in the chamber.

56. The apparatus of claim 54 wherein the test controller includes an encoder generating an encoded test control signal output by the transponder.

57. A method for manufacturing a semiconductor device, comprising:

fabricating a plurality of devices on a semiconductor wafer;

performing built-in self testing of each of the devices by coupling power and control signals to the wafer via an RF signal;

testing the devices; and

separating the devices from the wafer.

58. The method of claim 57 wherein the step of performing comprises the steps of:

providing the wafer into a burn-in chamber; and

outputting a power and a test initiation signal to a wafer via a wireless signal.

59. The method of claim 58 wherein said step of outputting includes outputting a signal initiating a device stress test sequence on the wafer.

60. The method of claim 59 wherein the step of outputting comprises generating an RF signal in the chamber.

61. The method of claim 57 wherein the step of performing includes heating the wafer in the chamber.

62. A non volatile memory system, comprising:

an array of storage elements and control circuitry;

a BIST circuit coupled to the control circuitry; and

an RF interface coupled to the BIST circuit.