Apparatus and method for time-to-digital conversion and jitter-measuring apparatus using the same

• US 20060132340A1
• Filed: 12/19/2005
• Published: 06/22/2006
• Est. Priority Date: 12/22/2004
• Status: Abandoned Application

• Current Assignee: Spirox Corporation
• Original Assignee: Spirox Corporation
• Inventors: Lin, Chun Wei
• Application Number:
  US11/305,168
• Publication Number:
  US 20060132340A1
• Time in Patent Office: Days
• US Class Current: 341/120
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60

Abstract

A time-to-digital conversion apparatus reduces the pulse width of a signal to be tested by introducing the signal through a plurality of shrinking cells cascaded until the reduced pulse width cannot drive the next shrinking cell, to generate a group of digital output codes representative of a binary code. The apparatus operates with a clock signal and comprises a shrinking cell group converting the signal to be tested to a plurality of first digital output codes, and a latch cell group receiving the first digital output codes and generating a plurality of second digital output codes which can be converted to a binary code. The time-to-digital conversion apparatus could be utilized in a jitter-measuring apparatus, which converts the jitter of a signal of analog form to a group of digital codes. The digital codes represent a time width of cycle-to-cycle jitter of the signal.

Claims

1. A time-to-digital conversion apparatus, which is operated with a clock signal, to convert a signal to be tested to a digital code, comprising:

a shrinking cell group converting the signal to be tested to a plurality of first digital output codes, the shrinking cell group including a plurality of shrinking cells connected in series to form a multi-stage shrinking cell, each of the shrinking cells generating one of the first digital output codes; and

a latch cell group including a plurality of latch cells, each latch cell being connected to the corresponding shrinking cell, each latch cell receiving and latching the first digital output code to generate a second digital output code.

2. The time-to-digital conversion apparatus according to claim 1, wherein a pulse width of the signal to be tested is reduced by a resolution after the signal to be tested passes each shrinking cell until the pulse width cannot drive the next shrinking cell.

3. The time-to-digital conversion apparatus according to claim 2, wherein the shrinking cell comprises:

a first CMOS inverter receiving an input signal to generate a middle signal;

a second CMOS inverter receiving the middle signal to generate an output signal; and

an adjustment unit receiving the middle signal and the output signal and using a control signal to adjust the resolution.

4. The time-to-digital conversion apparatus according to claim 3, wherein the input signal of the first-stage shrinking cell is the signal to be tested.

5. The time-to-digital conversion apparatus according to claim 3, wherein the adjustment unit comprises:

a PMOS having a first terminal to receive the output signal, a second terminal to receive a power source, and a third terminal to receive the middle signal; and

an NMOS having a fourth terminal connected to the first terminal to receive the output signal, a fifth terminal connected to the third terminal to receive the middle signal, and a sixth terminal to receive the control signal.

6. The time-to-digital conversion apparatus according to claim 5, wherein the latch cell receives the corresponding first digital output code and outputs a signal with the same level as that of the corresponding first digital output code.

7. The time-to-digital conversion apparatus according to claim 5, wherein the latch cell is a flip-flop including a clock port connected to the corresponding first digital output code, and an input port connected to the power source.

8. The time-to-digital conversion apparatus according to claim 1, wherein the second digital output code is expressed in a thermometer code.

9. The time-to-digital conversion apparatus according to claim 1, wherein the second digital output code is conditioned by a priority encoder to convert the second digital output code to at least one third digital output code which is stored in an output latch unit and is outputted whenever the output latch unit receives a trigger signal.

10. The time-to-digital conversion apparatus according to claim 9, wherein the third digital output code is a binary code.

11. A jitter-measuring apparatus, comprising:

an input controller dividing the frequency of a first clock signal by an odd number down to be a second clock signal, and generating a third clock signal with a time delay to the second clock signal;

a sample and hold circuit converting a first signal with a first pulse width to a second signal with a second pulse width in the light of the level of the third clock signal;

a pulse modulation unit converting the second signal to a third signal with a third pulse width by operating with a threshold voltage;

a pulse shrinking unit converting the third signal with the third pulse width to a fourth signal with a fourth pulse width;

a time-to-digital apparatus converting the fourth signal to at least one second digital output code; and

a latch controller using the second clock signal from the input controller to generate a reset signal to the time-to-digital conversion apparatus and generate a trigger signal.

12. The jitter-measuring apparatus according to claim 11, wherein the threshold voltage is less than 20% or larger than 80% of a power source.

13. The jitter-measuring apparatus according to claim 11, wherein the pulse shrinking unit comprises:

inverters of even number connected in series, receiving the third signal; and

an XNOR logic gate connected to the end of the inverters, receiving the third signal to generate the fourth signal.

14. The jitter-measuring apparatus according to claim 11, wherein the time-to-digital apparatus comprises:

a shrinking cell group converting the fourth signal to a plurality of first digital output codes, the shrinking cell group including a plurality of shrinking cells connected in series to form a multi-stage shrinking cell, each of the shrinking cells generating one of the first digital output codes; and

a latch cell group including a plurality of latch cells, each latch cell being connected to the corresponding shrinking cell, each latch cell receiving and latching the first digital output code to generate the second digital output code.

15. The jitter-measuring apparatus according to claim 14, wherein a pulse width of the fourth signal is reduced by a resolution after the fourth signal passes each shrinking cell until the pulse width cannot drive the next shrinking cell.

16. The jitter-measuring apparatus according to claim 15, wherein the shrinking cell comprises:

a first CMOS inverter receiving an input signal to generate a middle signal;

a second CMOS inverter receiving the middle signal to generate an output signal; and

an adjustment unit receiving the middle signal and the output signal and using a control signal to adjust the resolution.

17. The jitter-measuring apparatus according to claim 16, wherein the input signal of the first-stage shrinking cell is the fourth signal.

18. The jitter-measuring apparatus according to claim 16, wherein the adjustment unit comprises:

a PMOS having a first terminal to receive the output signal, a second terminal to receive a power source, and a third terminal to receive the middle signal; and

an NMOS having a fourth terminal connected to the first terminal to receive the output signal, a fifth terminal connected to the third terminal to receive the middle signal, and a sixth terminal to receive the control signal.

19. The jitter-measuring apparatus according to claim 18, wherein the latch cell receives the corresponding first digital output code and outputs a signal with the same level as that of the corresponding first digital output code.

20. The jitter-measuring apparatus according to claim 18, wherein the latch cell is a flip-flop including a clock port connected to the corresponding first digital output code, and an input port connected to the power source.

21. The jitter-measuring apparatus according to claim 11, wherein the second digital output code is expressed in a thermometer code.

22. The jitter-measuring apparatus according to claim 15, wherein the second digital output code is conditioned by a priority encoder to convert the second digital output code to at least one third digital output code which is stored in an output latch unit and is outputted whenever the output latch unit receives the trigger signal.

23. The jitter-measuring apparatus according to claim 22, wherein the trigger signal comes from the latch controller.

24. The jitter-measuring apparatus according to claim 22, wherein the third digital output code is a binary code.

25. The jitter-measuring apparatus according to claim 24, wherein a pulse width of the fourth signal is reduced by the resolution after the fourth signal passes each shrinking cell until the pulse width cannot drive the next shrinking cell, and the product of the binary code and the resolution represents the time width of cycle-to-cycle jitter of the first signal.

26. A jitter-measuring apparatus, comprising:

an input controller converting a first signal to a sample and hold control signal;

a sample and hold circuit converting the first signal to a second signal with a second pulse width by operating with the sample and hold control signal;

a pulse modulation unit converting the second signal to a third signal with a third pulse width by operating with a threshold voltage;

an adjustable pulse shrinking unit reducing the third pulse width to generate a fourth signal with a fourth pulse width;

a time-to-digital conversion apparatus converting the fourth signal to at lease one second digital output code; and

a latch controller receiving a first control signal from the adjustable pulse shrinking unit to generate a reset signal to the time-to-digital conversion apparatus and generate a trigger signal.

27. The jitter-measuring apparatus according to claim 26, wherein the threshold voltage is less than 20% or larger than 80% of a power source.

28. The jitter-measuring apparatus according to claim 26, wherein the adjustable pulse shrinking unit comprises:

an inverter string comprising some even number of inverters disposed in series, receiving the third signal, including two fixed inverters disposed at opposing ends of the inverter string and an even number of adjustable inverters disposed between the two fixed inverters; and

an XNOR logic gate receiving the third signal and the output of the inverter string to generate the fourth signal, wherein the fourth pulse width is adjustable by a second control signal.

29. The jitter-measuring apparatus according to claim 26, wherein the time-to-digital conversion apparatus comprises:

a shrinking cell group converting the fourth signal to a plurality of first digital output codes, the shrinking cell group including a plurality of shrinking cells connected in series to form a multi-stage shrinking cell, each of the shrinking cells generating one of the first digital output codes; and

a latch cell group including a plurality of latch cells, each latch cell being connected to the corresponding shrinking cell, each latch cell receiving and latching one of the first digital output codes to generate the second digital output code.

30. The jitter-measuring apparatus according to claim 29, wherein a pulse width of the fourth signal is reduced by a resolution after the fourth signal passes each shrinking cell until the pulse width cannot drive the next shrinking cell.

31. The jitter-measuring apparatus according to claim 30, wherein the shrinking cell comprises:

a first CMOS inverter receiving an input signal to generate a middle signal;

a second CMOS inverter receiving the middle signal to generate an output signal; and

an adjustment unit receiving the middle signal and the output signal and using a third control signal to adjust the resolution.

32. The jitter-measuring apparatus according to claim 31, wherein the latch cell receives the corresponding first digital output code and outputs a signal with the same level as that of the corresponding first digital output code.

33. The jitter-measuring apparatus according to claim 31, wherein the latch cell is a flip-flop including a clock port receiving the corresponding first digital output code, and an input port connected to a power source.

34. The jitter-measuring apparatus according to claim 26, wherein the second digital output code is expressed in a thermometer code.

35. The jitter-measuring apparatus according to claim 31, wherein the second digital output code is conditioned by a priority encoder to convert the second digital output code to at least one third digital output code which is stored in an output latch unit and is outputted whenever the output latch unit receives the trigger signal.

36. The jitter-measuring apparatus according to claim 35, wherein the trigger signal is generated by the latch controller.

37. The jitter-measuring apparatus according to claim 35, wherein the third digital output code is expressed as a binary code, and the product of the binary code and the resolution represents the pulse width of cycle-to-cycle jitter of the first signal.

38. A method of time-to-digital conversion comprising the steps of:

shrinking a pulse width of a signal to be tested successively by a resolution to generate a plurality of first digital output codes; and

latching the plurality of the first digital output codes to generate a plurality of second digital output codes.

39. The method of time-to-digital conversion according to claim 38, wherein the plurality of second digital output codes are expressed in thermometer codes.

40. The method of time-to-digital conversion according to claim 38, further comprising the step of converting the plurality of second digital output codes to at least one third digital output code in a binary code.

41. The method of time-to-digital conversion according to claim 40, wherein the third digital output code is outputted by a trigger signal.

42. The method of time-to-digital conversion according to claim 38, wherein the pulse width of the signal to be tested covers the edges of another signal to be tested.