Power core devices and methods of making thereof

• US 20060133057A1
• Filed: 11/30/2005
• Published: 06/22/2006
• Est. Priority Date: 12/21/2004
• Status: Active Grant

• Current Assignee: Chemtron Research LLC (Intellectual Ventures LLC)
• Original Assignee: E. I. du Pont de Nemours and Company (Corteva, Inc.)
• Inventors: Sreeram, Attiganal N., Banerji, Sounak, Amey, Daniel Irwin Jr., Borland, William J., McGregor, David Ross, Dietz, Karl Hartmann
• Granted Patent: US 7,778,038 B2
• Time in Patent Office: Days
• US Class Current: 361/763
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 1/186 manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/10636 Leadless chip, e.g. chip capacitor or resistor
• CPC Class Codes: H05K 3/4641 having integrally laminated metal sheets or special power cores
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.

Claims

1. A power core comprising:

at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and

at least one planar capacitor laminate;

wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and

wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.

2. The power core of claim 1 wherein said planar capacitor laminate comprises an organic dielectric layer.

3. The power core of claim 1 wherein said planar capacitor laminate comprises a ceramic dielectric layer.

4. The power core of claim 1 wherein said planar capacitor laminate comprises a ceramic material filled organic dielectric layer wherein the ceramic material of said layer has a dielectric constant of greater than 500.

5. The power core of claim 1 wherein said planar capacitor dielectric laminate comprises a ceramic material filled organic dielectric layer wherein the ceramic material of said layer has a dielectric constant of less than 500.

6. The power core of claim 1 wherein said planar capacitor laminate is a copper-dielectric-copper laminate.

7. The power core of claim 6 wherein said copper-dielectric-copper laminate comprises one or more dielectric layers selected from an organic layer, a ceramic-filled organic layer, a ceramic layer, and mixtures thereof.

8. A method for making a power core structure comprising;

providing a planar capacitor laminate having at least one patterned side;

providing a metal foil;

laminating said metal foil to the patterned side of said planar capacitor laminate;

creating lands and via pads on said metal foil;

attaching at least one SMT discrete chip capacitor to said lands on said metal foil; and

connecting said at least one SMT discrete chip capacitor in parallel to said planar capacitor laminate.

10. The method of claim 8 wherein signal lines are incorporated and interconnected on the same layer as said SMT discrete chip capacitor layer.

11. The method of claim 8 wherein resistors are incorporated and interconnected on the same layer as said SMT discrete chip capacitor layer.

12. The method of claim 8 wherein a resistive element is incorporated into said planar capacitor laminate to form a resistor capacitor element.

13. The method of claim 8 wherein said planar capacitor laminate is formed by the method comprising:

providing a first metallic foil;

providing a first dielectric layer on said first metallic foil forming a first coated metallic foil;

providing a second metallic foil;

providing a second dielectric layer on said second metallic foil forming a second coated metallic foil; and

laminating said first and second coated metallic foils together.

14. The method of claim 8 wherein said planar capacitor laminate is formed by the method comprising:

providing a first metallic foil;

providing a dielectric layer on said first metallic foil thus forming a coated metallic foil with a dielectric layer side and a metallic foil side;

providing a second metallic foil; and

laminating said second metallic foil to said dielectric layer side of said coated metallic foil.

15. The method of claim 8 wherein said planar capacitor laminate is formed by the method comprising:

providing a first metallic foil;

providing a first dielectric layer having a first side and a second side;

providing a second metallic foil; and

simultaneously laminating said first metallic foil to said first side of said dielectric layer and said second metallic foil to said second side of said dielectric layer.

16. The method of claim 8 wherein said planar capacitor laminate is formed by the method comprising:

providing a first metallic foil;

providing a first dielectric layer on said first metallic foil and firing said dielectric thereby forming a first coated metallic foil; and

forming a first electrode over the fired dielectric.

17. The method of claim 8 wherein said planar capacitor comprises a first metal layer, a dielectric layer, and second metal layer and wherein at least one metal layer is formed by a method selected from screen printing, and sputtering and plating.

9. A method for making a power core structure comprising:

providing a planar capacitor laminate having a first patterned side and a second patterned side;

providing a metal foil;

laminating said metal foil to one said patterned side of said planar capacitor laminate;

creating lands and via pads on said metal foil;

attaching at least one SMT discrete chip capacitor to said lands on said metal foil; and

connecting said at least one SMT discrete chip capacitor in parallel to said planar capacitor laminate.

18. A device comprising a power core wherein said power core comprises:

at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and

at least one planar capacitor laminate;

wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and

wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate; and

wherein said power core is interconnected to at least one signal layer.

19. The device of claim 18 wherein said SMT discrete chip capacitor comprises at least a first and a second electrode.

20. The device of claim 19 wherein said first electrode and second electrode are connected to at least one power terminal of a semiconductor device.

21. The device of claim 20 wherein the semiconductor device is an integrated circuit.

22. The device of claim 18 comprising more than one signal layer wherein said signal layers are connected through conductive vias.

23. The device of claim 18 wherein said device is selected from an interposer, printed wiring board, multichip module, area array package, system-on-package, and system-in-package.

24. A method for making a device comprising;

providing a planar capacitor laminate having at least one patterned side;

providing a metal foil;

laminating said metal foil to the patterned side of said planar capacitor laminate;

creating lands and via pads on said metal foil;

attaching at least one SMT discrete chip capacitor to said lands on said metal foil;

connecting said at least one SMT discrete chip capacitor in parallel to said planar capacitor laminate forming a power core; and

forming at least one signal layer onto said power core.

26. The method of claims 24 or 25 wherein said signal layers are formed by applying a dielectric layer to one or both surfaces of said power core;

forming circuitry comprising one or more signal lines on said dielectric layer; and

forming a conductive interconnection between layers comprising said signal lines.

27. The method of claim 26 wherein said interconnection between layers is a conductive via.

28. The method of any one of claims 24 or 25 wherein additional passive components are connected to and external to said power core.

25. A method for making a device comprising:

providing a planar capacitor laminate having a first patterned side and a second patterned side;

providing a metal foil;

laminating said metal foil to one said patterned side of said planar capacitor laminate;

creating lands and via pads on said metal foil;

attaching at least one SMT discrete chip capacitor to said lands on said metal foil;

connecting said at least one SMT discrete chip capacitor in parallel to said planar capacitor laminate forming a power core; and

forming at least one signal layer onto said power core.