Power core devices and methods of making thereof
First Claim
Patent Images
1. A power core comprising:
- at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and
at least one planar capacitor laminate;
wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and
wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.
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Abstract
The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.
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Citations
28 Claims
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1. A power core comprising:
- at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and
at least one planar capacitor laminate;
wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and
wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate. - View Dependent Claims (2, 3, 4, 5, 6, 7)
- at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and
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8. A method for making a power core structure comprising;
- providing a planar capacitor laminate having at least one patterned side;
providing a metal foil;
laminating said metal foil to the patterned side of said planar capacitor laminate;
creating lands and via pads on said metal foil;
attaching at least one SMT discrete chip capacitor to said lands on said metal foil; and
connecting said at least one SMT discrete chip capacitor in parallel to said planar capacitor laminate. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
- providing a planar capacitor laminate having at least one patterned side;
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9. A method for making a power core structure comprising:
- providing a planar capacitor laminate having a first patterned side and a second patterned side;
providing a metal foil;
laminating said metal foil to one said patterned side of said planar capacitor laminate;
creating lands and via pads on said metal foil;
attaching at least one SMT discrete chip capacitor to said lands on said metal foil; and
connecting said at least one SMT discrete chip capacitor in parallel to said planar capacitor laminate.
- providing a planar capacitor laminate having a first patterned side and a second patterned side;
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18. A device comprising a power core wherein said power core comprises:
at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and
at least one planar capacitor laminate;
wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and
wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate; and
wherein said power core is interconnected to at least one signal layer.- View Dependent Claims (19, 20, 21, 22, 23)
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24. A method for making a device comprising;
- providing a planar capacitor laminate having at least one patterned side;
providing a metal foil;
laminating said metal foil to the patterned side of said planar capacitor laminate;
creating lands and via pads on said metal foil;
attaching at least one SMT discrete chip capacitor to said lands on said metal foil;
connecting said at least one SMT discrete chip capacitor in parallel to said planar capacitor laminate forming a power core; and
forming at least one signal layer onto said power core. - View Dependent Claims (26, 27, 28)
- providing a planar capacitor laminate having at least one patterned side;
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25. A method for making a device comprising:
- providing a planar capacitor laminate having a first patterned side and a second patterned side;
providing a metal foil;
laminating said metal foil to one said patterned side of said planar capacitor laminate;
creating lands and via pads on said metal foil;
attaching at least one SMT discrete chip capacitor to said lands on said metal foil;
connecting said at least one SMT discrete chip capacitor in parallel to said planar capacitor laminate forming a power core; and
forming at least one signal layer onto said power core.
- providing a planar capacitor laminate having a first patterned side and a second patterned side;
Specification