Apparatus and method for memory operations using address-dependent conditions

• US 20060133125A1
• Filed: 12/17/2004
• Published: 06/22/2006
• Est. Priority Date: 12/17/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Fasoli, Luca G., So, Kenneth K.
• Granted Patent: US 7,218,570 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.

Claims

1. An apparatus comprising:

a plurality of word lines and word line drivers;

a plurality of bit lines and bit line drivers;

a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and

circuitry operative to select a writing condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver.

2. The invention of claim 1, wherein the writing condition comprises a voltage, and wherein the circuitry selects less of a voltage to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.

3. The invention of claim 1, wherein the writing condition comprises a reference current, and wherein the circuitry selects a greater reference current to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.

4. The invention of claim 1, wherein the writing condition comprises both a voltage and a reference current, wherein the circuitry selects less voltage and a greater reference current to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.

5. The invention of claim 1, wherein the circuitry is operative to select a writing condition to apply to a memory cell based on the memory cell'"'"'s location with respect to a word line driver but not to a bit line driver.

6. The invention of claim 1, wherein the circuitry is operative to select a writing condition to apply to a memory cell based on the memory cell'"'"'s location with respect to a bit line driver but not to a word line driver.

7. The invention of claim 1, wherein the circuitry is operative to select a writing condition to apply to a memory cell based on the memory cell'"'"'s location with respect to both a word line driver and a bit line driver.

8. The invention of claim 1, wherein the circuitry is further operative to select a reading condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver.

9. The invention of claim 1, wherein the plurality of memory cells are organized into a plurality of zones, and wherein the circuitry is operative to select different writing conditions to apply to different zones.

10. The invention of claim 9, wherein each zone comprises a plurality of word lines.

11. The invention of claim 9, wherein each zone comprises a plurality of bit lines.

12. The invention of claim 1, wherein each memory cell is associated with an address, and wherein the circuitry is operative to select a writing condition to apply to a memory cell based on the memory cell'"'"'s address.

13. The invention of claim 1, wherein at least some of the plurality of memory cells comprise write-once memory cells.

14. The invention of claim 1, wherein at least some of the plurality of memory cells comprise write-many memory cells.

15. The invention of claim 1, wherein at least some of the plurality of memory cells comprise few-time programmable memory cells

16. The invention of claim 1, wherein the plurality of memory cells are organized in a plurality of layers stacked vertically above one another above a single substrate.

17. The invention of claim 1, wherein the plurality of memory cells are organized in a single layer.

41. The invention of claim 9, wherein each zone comprises a plurality of word lines and bit lines.

18. An apparatus comprising:

a plurality of word lines and word line drivers;

a plurality of bit lines and bit line drivers;

a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and

circuitry operative to select a reading condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver.

19. The invention of claim 18, wherein the reading condition comprises a voltage, and wherein the circuitry selects less of a voltage to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.

20. The invention of claim 18, wherein the reading condition comprises a reference current, and wherein the circuitry selects a greater reference current to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.

21. The invention of claim 18, wherein the reading condition comprises both a voltage and a reference current, wherein the circuitry select less of a voltage and a greater reference current to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.

22. The invention of claim 18, wherein the circuitry is operative to select a reading condition to apply to a memory cell based on the memory cell'"'"'s location with respect to a word line driver but not to a bit line driver.

23. The invention of claim 18, wherein the circuitry is operative to select a reading condition to apply to a memory cell based on the memory cell'"'"'s location with respect to a bit line driver but not to a word line driver.

24. The invention of claim 18, wherein the circuitry is operative to select a reading condition to apply to a memory cell based on the memory cell'"'"'s location with respect to both a word line driver and a bit line driver.

25. The invention of claim 18, wherein the plurality of memory cells are organized into a plurality of zones, and wherein the circuitry is operative to select different reading conditions to apply to different zones.

26. The invention of claim 25, wherein each zone comprises a plurality of word lines.

27. The invention of claim 25, wherein each zone comprises a plurality of bit lines.

28. The invention of claim 18, wherein each memory cell is associated with an address, and wherein the circuitry is operative to select a reading condition to apply to a memory cell based on the memory cell'"'"'s address.

29. The invention of claim 18, wherein at least some of the plurality of memory cells comprise write-once memory cells.

30. The invention of claim 18, wherein at least some of the plurality of memory cells comprise write-many memory cells.

31. The invention of claim 18, wherein at least some of the plurality of memory cells comprise few-time programmable memory cells.

32. The invention of claim 18, wherein the plurality of memory cells are organized in a plurality of layers stacked vertically above one another above a single substrate.

33. The invention of claim 18, wherein the plurality of memory cells are organized in a single layer.

42. The invention of claim 25, wherein each zone comprises a plurality of word lines and bit lines.

34. An apparatus comprising:

a plurality of word lines and word line drivers;

a plurality of bit lines and bit line drivers;

a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and

circuitry operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to one or both of a word line driver and a bit line driver.

35. The invention of claim 34, wherein the plurality of memory cells are organized into a plurality of zones, and wherein the circuitry is operative to select a number of memory cells to be programmed in parallel based on a memory cell'"'"'s zone.

36. The invention of claim 34, wherein at least some of the plurality of memory cells comprise write-once memory cells.

37. The invention of claim 34, wherein at least some of the plurality of memory cells comprise write-many memory cells.

38. The invention of claim 34, wherein at least some of the plurality of memory cells comprise few-time programmable memory cells.

39. The invention of claim 34, wherein the plurality of memory cells are organized in a plurality of layers stacked vertically above one another above a single substrate.

40. The invention of claim 34, wherein the plurality of memory cells are organized in a single layer.

43. The invention of claim 35, wherein each zone comprises a plurality of word lines.

44. The invention of claim 35, wherein each zone comprises a plurality of bit lines.

45. The invention of claim 35, wherein each zone comprises a plurality of word lines and bit lines.