RFID tags storing component configuration data in non-volatile memory and methods

• US 20060133140A1
• Filed: 12/17/2004
• Published: 06/22/2006
• Est. Priority Date: 12/17/2004
• Status: Abandoned Application

• Current Assignee: Impinj, Inc., Microsoft Corporation
• Original Assignee: Impinj, Inc.
• Inventors: Oliver, Ronald A., Pesavento, Alberto, Hyde, John D., Gutnik, Vadim, Cooper, Scott Anthony, Dressler, David D., Sundstrom, Kurt Eugene
• Application Number:
  US11/015,293
• Publication Number:
  US 20060133140A1
• Time in Patent Office: Days
• US Class Current: 365/185.80
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

An RFID tag has a Non Volatile Memory (NVM) array that can store data in a way that survives loss of power. The data is configuration data that controls the operation of an operational component of the tag. A performance of the operational component is thus adjusted according to the configuration data, and the adjustment is retained.

Claims

1. An RFID tag circuit comprising:

a non-volatile memory (NVM) memory array having a plurality of NVM storage cells that are addressable in terms of at least one of a row and a column, at least a first one of the cells being adapted to store configuration data in a way that survives loss of power; and

an operational component adapted to operate based on the configuration data.

2. The circuit of claim 1, further comprising:

another NVM memory array having cells that are addressable in terms of at least one of a row and a column, at least some of the cells of the other array being adapted to store data in a way that survives loss of power.

3. The circuit of claim 1, wherein

the configuration data is at least one logical bit.

4. The circuit of claim 1, wherein

a value for the configuration data is encoded in an amount of charge stored in a device.

5. The circuit of claim 1, wherein

the configuration data is input in the operational component directly from the first cell.

6. The circuit of claim 1, wherein

the configuration data is first input in a binary output circuit from the first cell, and then it is input in the operational component from the binary output circuit.

7. The circuit of claim 6, wherein

the binary output circuit is a logic circuit.

8. The circuit of claim 6, wherein

the binary output circuit includes one of a buffer and a latch.

9. The circuit of claim 1, wherein

the operational component inputs the configuration data responsive to a command signal.

10. The circuit of claim 9, wherein

the command signal is a reset signal.

11. The circuit of claim 9, wherein

the command signal is received during testing.

12. The circuit of claim 11, wherein

the command signal is received while the circuit is formed in a wafer segment comprising a plurality of additional RFID tag circuits.

13. The circuit of claim 11, wherein

testing is performed by a probe, and

the command signal is generated by an action of the probe.

14. The circuit of claim 1, wherein

the operational component is a power-on reset circuit.

15. The circuit of claim 1, wherein

the operational component is a demodulator.

16. The circuit of claim 1, wherein

the operational component is a modulator.

17. The circuit of claim 1, wherein

the operational component is an antenna port tuner.

18. The circuit of claim 1, wherein

the operational component is a rectifier.

19. The circuit of claim 1, wherein

the operational component is a power management unit.

20. The circuit of claim 1, wherein

the operational component is a random number generator.

21. The circuit of claim 1, wherein

the operational component is an oscillator.

22. The circuit of claim 1, wherein

the operational component is a state machine of the tag.

23. The circuit of claim 1, wherein

the operational component is a state machine of the NVM memory array.

24. The circuit of claim 1, wherein

the operational component is a state machine that includes a multiplexer.

25. The circuit of claim 1, further comprising:

a controller adapted to program the configuration data in the first cell.

26. The circuit of claim 25, wherein

the configuration data is input in the operational component directly from the first cell.

27. The circuit of claim 25, wherein

the configuration data is first input in the controller from the first cell, and then it is input in the operational component from the controller.

28. The circuit of claim 25, wherein

the configuration data is first input in a binary output circuit from the first cell, and then it is input in the operational component from the binary output circuit.

29. The circuit of claim 28, wherein

the binary output circuit is a logic circuit.

30. The circuit of claim 28, wherein

the binary output circuit includes one of a buffer and a latch.

31. The circuit of claim 25, wherein

the controller is adapted to determine the configuration data to program in the first cell.

32. The circuit of claim 31, further comprising:

an antenna for receiving a wireless signal, and

wherein determining is performed from the received wireless signal.

33. The circuit of claim 31, wherein

the controller is adapted to sense a performance of the operational component, and

wherein determining is performed so as to adjust the performance.

34. The circuit of claim 25, wherein

the operational component is a power-on reset circuit.

35. The circuit of claim 25, wherein

the operational component is a demodulator.

36. The circuit of claim 25, wherein

the operational component is a modulator.

37. The circuit of claim 25, wherein

the operational component is an antenna port tuner.

38. The circuit of claim 25, wherein

the operational component is a rectifier.

39. The circuit of claim 25, wherein

the operational component is a power management unit.

40. The circuit of claim 25, wherein

the operational component is a random number generator.

41. The circuit of claim 25, wherein

the operational component is an oscillator.

42. The circuit of claim 25, wherein

the operational component is a state machine.

43. The circuit of claim 42, wherein

the operational component is a state machine of the NVM memory array.

44. The circuit of claim 42, wherein

the operational component is a state machine of the controller.

45. The circuit of claim 42, wherein

the state machine includes a multiplexer.

46. The circuit of claim 42, wherein

the configuration data can encode one of two values, a first one of the two values indicating that a backscatter continuously feature is available, and a second one of the two values indicating that it is not.

47. The circuit of claim 42, wherein

the configuration data causes the tag to ignore a command by a reader to backscatter continuously.

48. The circuit of claim 42, wherein

the configuration data causes the tag to react to a command by a reader to backscatter continuously.

49. The circuit of claim 42, wherein

the configuration data causes the tag to be in a state of backscattering continuously.

50. The circuit of claim 1, wherein

the first cell uses a mechanism for nonvolatile storage of information selected from the group consisting of magnetoresistive, ferroelectric, phase-change, and dielectric.

51. The circuit of claim 1, wherein

the first cell includes a floating gate of a floating-gate transistor, and

the configuration data is stored in terms of a variable amount of charge on the floating gate.

52. The circuit of claim 51, wherein

the floating-gate transistor is a transistor selected from the group consisting of:

nFET, pFET, FinFET, and multi-gate FET.

53. The circuit of claim 51, wherein

the amount of charge may be changed using Fowler-Nordheim tunneling.

54. The circuit of claim 51, wherein

the amount of charge may be changed using bidirectional Fowler-Nordheim tunneling.

55. The circuit of claim 51, wherein

the amount of charge may be changed using hot-electron injection.

56. The circuit of claim 51, wherein

the amount of charge may be changed using direct tunneling.

57. The circuit of claim 51, wherein

the amount of charge may be changed using hot-hole injection.

58. The circuit of claim 51, wherein

the amount of charge may be changed using ultraviolet radiation exposure.

59. The circuit of claim 1, wherein

the operational component includes a configurable circuit adapted to exhibit a characteristic that varies according to the configuration data.

60. The circuit of claim 59, wherein

the configurable circuit includes an ON/OFF switch.

61. The circuit of claim 59, wherein

the configurable circuit includes a state machine.

62. The circuit of claim 59, wherein

the variable characteristic is an operative impedance.

63. The circuit of claim 62, wherein

the operational component includes an impedance component, and

the configurable circuit includes a switch for controlling whether the impedance component will be part of the operative impedance.

64. A device comprising:

means for generating an address for a tag non-volatile memory (NVM) array in terms of at least one of a row and a column;

means for outputting, in response to the address, configuration data stored in the array in a way that survives loss of power; and

means for operating a tag operational component as controlled by the output configuration data.

65. The device of claim 64, further comprising:

means for latching the configuration data.

66. The device of claim 64, wherein

the address is generated responsive to a command signal.

67. The device of claim 64, further comprising:

means for programming the configuration data in the array.

68. The device of claim 67, further comprising:

means for determining the configuration data to program in the array.

69. A method for an RFID tag circuit comprising:

generating an address for a tag non-volatile memory (NVM) array in terms of at least one of a row and a column;

outputting, in response to the address, configuration data stored in the array in a way that survives loss of power; and

operating a tag operational component as controlled by the output configuration data.

70. The method of claim 69, wherein

the operational component includes a configurable circuit,

the component is operated as controlled by an exhibited characteristic of the configurable circuit, and

the characteristic is variable and dependent on the configuration data.

71. The method of claim 69, wherein

the operational component is one of a power-on reset circuit, a demodulator, a modulator, an antenna port tuner, a rectifier, a power management unit, a random number generator, an oscillator, and a state machine.

72. The method of claim 69, wherein

the configuration data causes the tag to ignore a command by a reader to backscatter continuously.

73. The method of claim 69, wherein

the configuration data causes the tag to react to a command by a reader to backscatter continuously.

74. The method of claim 69, wherein

the configuration data causes the tag to be in a state of backscattering continuously.

75. The method of claim 74, further comprising:

measuring a backscattered power of the tag while it is continuously backscattering.

76. The method of claim 69, wherein

the configuration data is input in a binary output circuit, and

the tag operational component receives an output of the binary output circuit.

77. The method of claim 69, further comprising:

latching the configuration data.

78. The method of claim 69, further comprising:

cutting a wafer segment into a chip that includes the circuit.

79. The method of claim 69, wherein

the address is generated responsive to a command signal.

80. The method of claim 79, wherein

the command signal is a reset signal.

81. The method of claim 79, wherein

the command signal is generated responsive to a test probe.

82. The method of claim 69, further comprising:

programming the configuration data in the array.

83. The method of claim 82, further comprising:

determining the configuration data to program in the array.

84. The method of claim 83, further comprising:

receiving a wireless signal, and

wherein determining is performed from the received wireless signal.

85. The method of claim 83, further comprising:

receiving a signal from a testing device, and

wherein determining is performed from the received signal.

86. The method of claim 83, further comprising:

sensing a performance of the operational component, and

wherein determining is performed so as to adjust the performance.