RFID tags with electronic fuses for storing component configuration data

• US 20060133175A1
• Filed: 12/17/2004
• Published: 06/22/2006
• Est. Priority Date: 12/17/2004
• Status: Active Grant

• Current Assignee: Impinj, Inc., Microsoft Corporation
• Original Assignee: Impinj, Inc.
• Inventors: Oliver, Ronald A., Pesavento, Alberto, Hyde, John D., Gutnik, Vadim, Cooper, Scott Anthony, Dressler, David D., Sundstrom, Kurt Eugene
• Granted Patent: US 7,307,529 B2
• Time in Patent Office: Days
• US Class Current: 365/225.700
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

An RFID tag has a fuse that is adapted to store configuration data in a way that survives loss of power. The fuse can be one time programmable or many times programmable, and be implemented with a non-volatile memory. The configuration data becomes available to an operational component of the tag, such as at power up, controlling its performance.

Claims

1. An RFID tag circuit comprising:

a fuse adapted to store configuration data in a way that survives loss of power;

an operational component adapted to operate based on the configuration data; and

a non-volatile memory (NVM) memory array distinct from the fuse and having a plurality of NVM cells that are addressable in terms of a row and a column and are adapted to store data in a way that survives loss of power.

2. The circuit of claim 1, wherein

the fuse is one-time programmable.

3. The circuit of claim 1, wherein

the fuse is multiple-times programmable.

4. The circuit of claim 1, wherein

the fuse is part of the operational component.

5. The circuit of claim 1, further comprising:

another operational component, and

wherein the fuse is part of the other operational component.

6. The circuit of claim 1, wherein

a value for the configuration data is encoded in an amount of charge stored in a device.

7. The circuit of claim 1, wherein

the configuration data is at least one logical bit.

8. The circuit of claim 1, wherein

the configuration data is input in the operational component directly from the fuse.

9. The circuit of claim 1, wherein

the configuration data is first input in the NVM memory array from the fuse, and then it is input in the operational component from the NVM memory array.

10. The circuit of claim 1, wherein

the operational component inputs the configuration data responsive to a command signal.

11. The circuit of claim 10, wherein

the command signal is a reset signal.

12. The circuit of claim 10, wherein

the command signal is a power-on reset signal.

13. The circuit of claim 10, wherein

the command signal is received during testing.

14. The circuit of claim 13, wherein

the command signal is received while the circuit is formed in a wafer segment comprising a plurality of additional RFID tag circuits.

15. The circuit of claim 13, wherein

testing is performed by a probe, and

the command signal is generated by an action of the probe.

16. The circuit of claim 1, wherein

the operational component is one of a power-on reset circuit, a demodulator, a modulator, an antenna port tuner, a rectifier, a power management unit, a random number generator, an oscillator, and a state machine.

17. The circuit of claim 1, further comprising:

a controller adapted to program the configuration data in the fuse.

18. The circuit of claim 17, wherein

the fuse is one-time programmable.

19. The circuit of claim 17, wherein

the fuse is multiple-times programmable.

20. The circuit of claim 17, wherein

the fuse is part of the operational component.

21. The circuit of claim 17, wherein

the fuse is part of the controller.

22. The circuit of claim 17, wherein

the configuration data is input in the operational component directly from the fuse.

23. The circuit of claim 17, wherein

the configuration data is first input in the NVM memory array from the fuse, and then it is input in the operational component from the NVM memory array.

24. The circuit of claim 17, wherein

the configuration data is first input in the controller from the fuse, and then it is input in the operational component from the controller.

25. The circuit of claim 17, wherein

the controller is adapted to determine the configuration data to program in the fuse.

26. The circuit of claim 25, further comprising:

an antenna for receiving a wireless signal, and

wherein determining is performed from the received wireless signal.

27. The circuit of claim 25, wherein

the controller is adapted to sense a performance of the operational component, and

wherein determining is performed so as to adjust the performance.

28. The circuit of claim 17, wherein

the operational component is a power-on reset circuit.

29. The circuit of claim 17, wherein

the operational component is a demodulator.

30. The circuit of claim 17, wherein

the operational component is a modulator.

31. The circuit of claim 17, wherein

the operational component is an antenna port tuner.

32. The circuit of claim 17, wherein

the operational component is a rectifier.

33. The circuit of claim 17, wherein

the operational component is a power management unit.

34. The circuit of claim 17, wherein

the operational component is a random number generator.

35. The circuit of claim 17, wherein

the operational component is an oscillator.

36. The circuit of claim 17, wherein

the operational component is a state machine.

37. The circuit of claim 36, wherein

the state machine includes a multiplexer.

38. The circuit of claim 17, wherein

the operational component is a state machine of the NVM memory array.

39. The circuit of claim 17, wherein

the operational component is a state machine of the controller.

40. The circuit of claim 17, wherein

the configuration data can encode one of two values, a first one of the two values indicating that a backscatter continuously feature is available, and a second one of the two values indicating that it is not.

41. The circuit of claim 17, wherein

the configuration data causes the tag to ignore a command by a reader to backscatter continuously.

42. The circuit of claim 17, wherein

the configuration data causes the tag to react to a command by a reader to backscatter continuously.

43. The circuit of claim 17, wherein

the configuration data causes the tag to be in a state of backscattering continuously.

44. The circuit of claim 1, wherein

the fuse includes a nonvolatile memory (NVM) element for storing the configuration data, and

the operational component includes a configurable circuit adapted to exhibit a characteristic that varies according to the configuration data.

45. The circuit of claim 44, wherein

the configurable circuit includes an ON/OFF switch.

46. The circuit of claim 44, wherein

the configurable circuit includes a state machine.

47. The circuit of claim 44, wherein

the NVM element uses a mechanism for nonvolatile storage of information selected from the group consisting of magnetoresistive, ferroelectric, phase-change, and dielectric.

48. The circuit of claim 44, wherein

the NVM element includes a first floating gate of a first floating-gate transistor, and

the configuration data is encoded in terms of a variable amount of charge stored on the first floating gate.

49. The circuit of claim 48, wherein

the transistor is a transistor selected from the group consisting of:

nFET, pFET, FinFET, and multi-gate FET.

50. The circuit of claim 48, wherein

the NVM element includes a second transistor that operates in a differential mode with the first transistor.

51. The circuit of claim 48, wherein

the amount of charge may be changed using Fowler-Nordheim tunneling.

52. The circuit of claim 48, wherein

the amount of charge may be changed using bidirectional Fowler-Nordheim tunneling.

53. The circuit of claim 48, wherein

the amount of charge may be changed using hot-electron injection.

54. The circuit of claim 48, wherein

the amount of charge may be changed using direct tunneling.

55. The circuit of claim 48, wherein

the amount of charge may be changed using hot-hole injection.

56. The circuit of claim 48, wherein

the amount of charge may be changed using ultraviolet radiation exposure.

57. The circuit of claim 44, wherein

the variable characteristic is an operative impedance.

58. The circuit of claim 57, wherein

the configuration data can take such values that the operative impedance is continuously variable.

59. The circuit of claim 58, wherein

the nonvolatile memory element includes a floating gate of a floating-gate transistor which is adapted to be in triode operation.

60. The circuit of claim 57, wherein

the configuration data can take such values that the operative impedance is discretely variable.

61. The circuit of claim 60, wherein

the operational component includes an impedance component, and

the fuse further includes a switch for controlling whether the impedance component will be part of the operative impedance.

62. The circuit of claim 61, wherein

the binary output circuit is a logic circuit.

63. The circuit of claim 1, wherein

the fuse includes a binary output circuit adapted to output a binary value dependent on the configuration data, and

the tag operational component receives an output of the binary output circuit.

64. The circuit of claim 63, wherein

the binary output circuit is a logic circuit.

65. The circuit of claim 63, wherein

the binary output circuit includes a buffer.

66. The circuit of claim 63, wherein

the binary output circuit is a latch.

67. The circuit of claim 66, wherein

the latch has two cross-coupled inverters.

68. The circuit of claim 63, wherein the binary output circuit includes

a master latch, and

a slave latch having a slave-latch input coupled to an output of the master latch.

69. The circuit of claim 68, wherein

the slave latch further has a slave-latch node configured to receive a slave-latch signal.

70. The circuit of claim 63, wherein

the fuse further includes a second nonvolatile memory element coupled to the binary output circuit.

71. The circuit of claim 63, wherein

the fuse further includes a capacitive element coupled to an output of the binary output circuit.

72. A device comprising:

means for inputting from a tag fuse programmed configuration data that is stored in the fuse in a way that survives loss of power, the fuse being distinct from a tag non-volatile memory (NVM) array that has a plurality of NVM cells that are addressable in terms of a row and a column and are adapted to store data in a way that survives loss of power; and

means for operating a tag operational component distinct from the tag fuse as controlled by the input configuration data.

73. The device of claim 72, wherein

the operational component includes a configurable circuit,

the component is operated as controlled by an exhibited characteristic of the configurable circuit, and

the characteristic is variable and dependent on the input configuration data.

74. The device of claim 72, wherein

the operational component is one of a power-on reset circuit, a demodulator, a modulator, an antenna port tuner, a rectifier, a power management unit, a random number generator, an oscillator, and a state machine.

75. The device of claim 72, further comprising:

means for latching the configuration data.

76. The device of claim 72, further comprising:

means for programming the configuration data in the fuse.

77. The device of claim 76, further comprising:

means for determining the configuration data to program in the fuse.

78. A method for an RFID tag circuit comprising:

inputting from a tag fuse programmed configuration data that is stored in the fuse in a way that survives loss of power, the fuse being distinct from a tag non-volatile memory (NVM) array that has a plurality of NVM cells that are addressable in terms of a row and a column and are adapted to store data in a way that survives loss of power;

operating a tag operational component distinct from the tag fuse as controlled by the input configuration data.

79. The method of claim 78, wherein

the operational component includes a configurable circuit,

the component is operated as controlled by an exhibited characteristic of the configurable circuit, and

the characteristic is variable and dependent on the input configuration data.

80. The method of claim 78, wherein

the operational component is one of a power-on reset circuit, a demodulator, a modulator, an antenna port tuner, a rectifier, a power management unit, a random number generator, an oscillator, and a state machine.

81. The method of claim 78, wherein

the configuration data causes the tag to ignore a command by a reader to backscatter continuously.

82. The method of claim 78, wherein

the configuration data causes the tag to react to a command by a reader to backscatter continuously.

83. The method of claim 78, wherein

the configuration data causes the tag to be in a state of backscattering continuously.

84. The method of claim 83, further comprising:

measuring a backscattered power of the tag while it is continuously backscattering.

85. The method of claim 78, wherein

the configuration data is input in a binary output circuit, and

the tag operational component receives an output of the binary output circuit.

86. The method of claim 78, further comprising:

cutting a wafer segment into a chip that includes the circuit.

87. The method of claim 78, wherein

the configuration data is input responsive to a command signal.

88. The method of claim 87, wherein

the command signal is a reset signal.

89. The method of claim 87, wherein

the command signal is a power-on reset signal.

90. The method of claim 87, wherein

the command signal is generated responsive to a test probe.

91. The method of claim 78, further comprising:

latching the configuration data.

92. The method of claim 78, further comprising:

programming the configuration data in the fuse.

93. The method of claim 92, further comprising:

determining the configuration data to program in the fuse.

94. The method of claim 93, further comprising:

receiving a wireless signal, and

wherein determining is performed from the received wireless signal.

95. The method of claim 93, further comprising:

receiving a signal from a testing device, and

wherein determining is performed from the received signal.

96. The method of claim 93, further comprising:

sensing a performance of the operational component, and

wherein determining is performed so as to adjust the performance.