Loop filter with gear shift for improved fractional-N PLL settling time
First Claim
1. A phase locked loop (PLL), comprising:
- a phase frequency detector operable to produce an error signal based upon a phase difference between a reference signal and a feedback signal;
a charge pump operable to produce an error current based upon the error signal;
a multi-mode loop filter operable to produce a control voltage based upon the error current;
an oscillator operable to produce an oscillation and the feedback signal in an undivided form based upon the control voltage; and
wherein the multi-mode loop filter operates in a startup mode characterized by a wide-band response with a fast settle time and in a steady state mode characterized by narrow-band response with improved filtering.
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Abstract
An integrated circuit radio frequency (RF) transmitter includes a phase locked loop having a multi-mode loop filter that is operable to provide wide band response with a fast settle time in a startup mode of operation and a relatively more narrow response with a longer settle time but with improved filtering in a steady state mode of operation according to one embodiment of the invention. The multi-mode loop filter includes, in one embodiment, selectable resistance circuitry for selecting between a plurality of resistance values based upon a two-state multi-mode control signal to provide the selected resistance values and selectable capacitance circuitry for selecting between a plurality of capacitance values based upon the two-state multi-mode control signal and for operatively coupling selected capacitors to selected resistors to provide the selected capacitance values. As a further aspect of the embodiment of the present invention, the multi-mode loop filter includes buffers for charging non-selected capacitors while not operationally coupled to the multi-mode loop filter to avoid additional settle time for the circuitry.
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Citations
20 Claims
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1. A phase locked loop (PLL), comprising:
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a phase frequency detector operable to produce an error signal based upon a phase difference between a reference signal and a feedback signal;
a charge pump operable to produce an error current based upon the error signal;
a multi-mode loop filter operable to produce a control voltage based upon the error current;
an oscillator operable to produce an oscillation and the feedback signal in an undivided form based upon the control voltage; and
wherein the multi-mode loop filter operates in a startup mode characterized by a wide-band response with a fast settle time and in a steady state mode characterized by narrow-band response with improved filtering. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method within a phase-locked loop (PLL), comprising:
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producing an error signal based upon a phase difference between a reference signal and a feedback signal;
producing an error current based upon the error signal;
producing a control voltage based upon the error current;
producing an oscillation based upon the control voltage; and
operating in a startup mode characterized by a wide-band response with a fast settle time and then operating in a steady state mode characterized by narrow-band response with improved filtering. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A loop filter, comprising:
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resistance circuitry coupled to receive an error current;
capacitance circuitry operatively coupled to the resistance circuitry wherein the capacitance and resistance for a loop filter having a specified bandwidth;
buffer circuitry, wherein the capacitance circuitry includes at least one capacitor selectively coupled to the buffer circuitry wherein the at least one capacitor is operatively coupled to reduce the specified bandwidth of the loop filter and to provide filtering in a steady state mode of operation of the loop filter and wherein the at least one capacitor is operatively decoupled from the loop filter in a startup mode of operation while receiving a charge from the buffer circuitry. - View Dependent Claims (20)
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Specification