Data integrity processing and protection techniques

• US 20060136619A1
• Filed: 12/16/2004
• Published: 06/22/2006
• Est. Priority Date: 12/16/2004
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Murray, Joseph, Tse, Gregory, Edirisooriya, Samantha
• Application Number:
  US11/017,183
• Publication Number:
  US 20060136619A1
• Time in Patent Office: Days
• US Class Current: 710/52
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Techniques to accelerate block guard processing of data by use of block guard units in a path between a source memory device and an originator of a data transfer request. The block guard unit may intercept the data transfer request and data transferred in response to the data transfer request. The block guard unit may utilize a cache to store information useful to verify block guards associated with the data.

Claims

1. A method comprising:

storing at least one context in a cache;

intercepting an access request transmitted to a source memory device;

intercepting data transferred by the source memory device in response to the access request;

selectively retrieving a context associated with the access request from a context cache based on availability of the context in the context cache;

forming a block guard based on the associated context;

selectively processing a block guard associated with the data based in part on the formed block guard; and

transferring the data to a destination memory device.

2. The method of claim 1, wherein the selectively retrieving a context associated with the access request from a context cache comprises:

determining whether the context is stored in the context cache; and

if the context is not stored in the context cache, requesting the context from a context memory;

3. The method of claim 1, wherein the selectively retrieving a context associated with the access request from a context cache comprises:

if the context is stored in the context cache and the access request is for a new I/O stream, requesting the context associated with the access request from a context memory.

4. The method of claim 1, wherein the selectively retrieving a context associated with the access request from a context cache comprises:

if the context is not stored in the context cache and the context cache is full, evicting a context from the context cache and requesting the context associated with the access request from a context memory.

5. The method of claim 1, wherein the selectively processing comprises:

verifying a cyclical redundancy check value in the block guard associated with the data based on the formed block guard.

6. The method of claim 1, wherein the selectively processing comprises:

verifying a cyclical redundancy check value in the block guard associated with the data based on the formed block guard; and

replacing the block guard associated with the formed block guard.

7. The method of claim 1, wherein the selectively processing comprises:

verifying a cyclical redundancy check value in the block guard associated with the data based on the formed block guard; and

appending the formed block guard to the data.

8. The method of claim 1, wherein the data includes at least a first and second portions and further comprising:

affixing the formed block guard to a first portion of the data; and

adjusting a destination address of the second portion of the data based on the size of the affixed block guard.

9. An apparatus comprising:

a block guard unit to intercept an access request transmitted to a source memory device and to intercept a data stream transferred by the source memory device in response to processing of the access request, wherein the block guard unit comprises;

a cache to store at least one context;

a control logic to determine whether a context associated with the access request is stored in the cache and to form a block guard based on the context provided by the cache;

a lane shifter to selectively shift the first valid byte of the data stream to a zero byte lane among data lanes;

a block guard computer to receive the data stream from the lane shifter and to selectively process a block guard associated with the data stream based in part on the formed block guard; and

a multiplexer to selectively transfer the data stream and the formed block guard.

10. The apparatus of claim 9, wherein for each data block in the data stream, the block guard computer computes a cyclical redundancy check value and compares the computed cyclical redundancy check value against the cyclical redundancy check value in the block guard associated with the data stream.

11. The apparatus of claim 9, wherein for each data block in the data stream, the block guard computer computes a cyclical redundancy check value and compares the computed cyclical redundancy check value against the cyclical redundancy check value in the block guard associated with the data stream and wherein the multiplexer replaces the block guard associated with the data stream with a block guard incorporating the computed cyclical redundancy check value.

12. The apparatus of claim 9, wherein for each data block in the data stream, the block guard computer computes a cyclical redundancy check value and compares the computed cyclical redundancy check value against the cyclical redundancy check value in the block guard associated with the data stream and wherein the multiplexer appends the computed cyclical redundancy check value in a block guard to the data stream.

13. The apparatus of claim 9, wherein the data stream includes first and second portions, wherein the multiplexer appends a block guard to the first portion, and wherein the control logic modifies a destination address of the second portion based on the size of the appended block guard.

14. The apparatus of claim 9, wherein if the cache stores the associated context, the cache provides the context.

15. The apparatus of claim 9, wherein if the cache does not store the associated context, the control logic requests a context memory to provide the context for storage into the cache and the cache provides the context.

16. The apparatus of claim 9, wherein if the cache does not store the associated context and the cache is full, the cache evicts a context and retrieves the associated context from context memory.

17. The apparatus of claim 9, wherein for a new data stream, the control logic requests a context memory to provide a replacement context for storage into the cache and the cache provides the replacement context as the associated context.

18. A system comprising:

a host system comprising a processor, a memory device, and an intercommunication device;

a local memory;

a storage device communicatively coupled to receive information from the local memory and provide information to the local memory;

an I/O system communicatively coupled to the intercommunication device and to provide information transfer between the local memory and the host system, wherein the I/O system includes;

an I/O processor to initiate and sending of access requests to transfer information; and

a block guard unit to intercept an access request transmitted to a source memory device and to intercept a data stream transferred by the source memory device in response to processing of the access request, wherein the block guard unit comprises;

a cache to store at least one context;

a control logic to determine whether a context associated with the access request is stored in the cache and to form a block guard based on the context provided by the cache;

a lane shifter to selectively shift the first valid byte of the data stream to a zero byte lane among data lanes;

a block guard computer to receive the data stream from the lane shifter and to selectively process a block guard associated with the data stream based in part on the formed block guard; and

a multiplexer to selectively transfer the data stream and the formed block guard.

19. The system of claim 18, further comprising a network interface communicatively coupled to the intercommunication device.

20. The system of claim 18, wherein the intercommunication device includes a PCI compatible bus.

21. The system of claim 18, wherein the intercommunication device includes a PCI express compatible bus.